alpha,arm,mips,power,riscv,sparc,x86,cpu: Get rid of ISA_HAS_DELAY_SLOT.

This constant is, first, a #define, and second only used in one place.

In that one place, it appears that the code it guards is no longer
necessary in general. It was originally written to avoid refetching a
block of data that you're still in, even if you've moved slightly
farther in it because you're skipping the next instruction due to an
annulled branch delay slot. In reality however, in SPARC, the one ISA
I'm aware of which has this sort of branching behavior, the PC state
object will correctly determine that no branch is happening in these
cases. Code lower down in the loop will then recompute where fetching
should continue based on the next PC, automatically skipping the
annulled branch slot without misinterpretting the gap as a branch.

This change therefore also removes this block of code.

Change-Id: I820ebc9df10aeb4fcb69c12f6a784e9ec616743c
Reviewed-on: https://gem5-review.googlesource.com/6821
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

diff --git a/src/arch/alpha/isa_traits.hh b/src/arch/alpha/isa_traits.hh
index 54b8003becac4465f013b09e98bef3178aa5b544..61688b5c8be155b3177db36e540c8bdfc6026850 100644 (file)
--- a/src/arch/alpha/isa_traits.hh
+++ b/src/arch/alpha/isa_traits.hh
@@ -45,9 +45,6 @@ using namespace LittleEndianGuest;
 
 StaticInstPtr decodeInst(ExtMachInst);
 
-// Alpha Does NOT have a delay slot
-#define ISA_HAS_DELAY_SLOT 0
-
 const Addr PageShift = 13;
 const Addr PageBytes = ULL(1) << PageShift;
 const Addr PageMask = ~(PageBytes - 1);

diff --git a/src/arch/arm/isa_traits.hh b/src/arch/arm/isa_traits.hh
index fa2779558e42ba3e81ca04ddba1673ffbd26c8d6..5763e7747dfe780085f54aaf03892caec5b018c6 100644 (file)
--- a/src/arch/arm/isa_traits.hh
+++ b/src/arch/arm/isa_traits.hh
@@ -57,9 +57,6 @@ namespace ArmISA
 
     StaticInstPtr decodeInst(ExtMachInst);
 
-    // ARM DOES NOT have a delay slot
-    #define ISA_HAS_DELAY_SLOT 0
-
     const Addr PageShift = 12;
     const Addr PageBytes = ULL(1) << PageShift;
     const Addr Page_Mask = ~(PageBytes - 1);

diff --git a/src/arch/mips/isa_traits.hh b/src/arch/mips/isa_traits.hh
index 7a1607183af850bdf00d88edf880b1392cdb0829..6e08c7e855b1ba8b36ee2165a466cb64d791f3b7 100644 (file)
--- a/src/arch/mips/isa_traits.hh
+++ b/src/arch/mips/isa_traits.hh
@@ -47,9 +47,6 @@ using namespace LittleEndianGuest;
 
 StaticInstPtr decodeInst(ExtMachInst);
 
-// MIPS DOES have a delay slot
-#define ISA_HAS_DELAY_SLOT 1
-
 const Addr PageShift = 13;
 const Addr PageBytes = ULL(1) << PageShift;
 const Addr Page_Mask = ~(PageBytes - 1);

diff --git a/src/arch/power/isa_traits.hh b/src/arch/power/isa_traits.hh
index 41a8d7d1bcd9742a3fb1f4bce9b17f4f5c1088e4..9afe6803a1f99ae4f204dce66a1057ca5e0d499f 100644 (file)
--- a/src/arch/power/isa_traits.hh
+++ b/src/arch/power/isa_traits.hh
@@ -48,9 +48,6 @@ using namespace BigEndianGuest;
 
 StaticInstPtr decodeInst(ExtMachInst);
 
-// POWER DOES NOT have a delay slot
-#define ISA_HAS_DELAY_SLOT 0
-
 const Addr PageShift = 12;
 const Addr PageBytes = ULL(1) << PageShift;
 const Addr Page_Mask = ~(PageBytes - 1);

diff --git a/src/arch/riscv/isa_traits.hh b/src/arch/riscv/isa_traits.hh
index 21e684a25836978027c9dfe82676dbd032f05780..abafad2e22da47faa2e382fbc52315597c395276 100644 (file)
--- a/src/arch/riscv/isa_traits.hh
+++ b/src/arch/riscv/isa_traits.hh
@@ -57,9 +57,6 @@ namespace RiscvISA
 
 using namespace LittleEndianGuest;
 
-// Riscv does NOT have a delay slot
-#define ISA_HAS_DELAY_SLOT 0
-
 const Addr PageShift = 12;
 const Addr PageBytes = ULL(1) << PageShift;
 

diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh
index 4f98f7580205b802f008e6e15b042fae40923cca..58d8437ad78a24f3c6f6dd7f00742dc45a591c7d 100644 (file)
--- a/src/arch/sparc/isa_traits.hh
+++ b/src/arch/sparc/isa_traits.hh
@@ -44,9 +44,6 @@ namespace SparcISA
 // This makes sure the big endian versions of certain functions are used.
 using namespace BigEndianGuest;
 
-// SPARC has a delay slot
-#define ISA_HAS_DELAY_SLOT 1
-
 // real address virtual mapping
 // sort of like alpha super page, but less frequently used
 const Addr SegKPMEnd  = ULL(0xfffffffc00000000);

diff --git a/src/arch/x86/isa_traits.hh b/src/arch/x86/isa_traits.hh
index 2b19b1ba7cc51d70fc93d6317c2affe6493fa0b2..158e2f9e43fb35433b540bb01751df9ab143f644 100644 (file)
--- a/src/arch/x86/isa_traits.hh
+++ b/src/arch/x86/isa_traits.hh
@@ -53,9 +53,6 @@ namespace X86ISA
     //are used.
     using namespace LittleEndianGuest;
 
-    // X86 does not have a delay slot
-#define ISA_HAS_DELAY_SLOT 0
-
     const Addr PageShift = 12;
     const Addr PageBytes = ULL(1) << PageShift;
 

diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index d8793426be16cfadf3b1ff77c0a3286b9dd98d7d..2e8ec67aef4f37df4b892df1347a58b8bfc0af36 100644 (file)
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -1277,17 +1277,6 @@ DefaultFetch<Impl>::fetch(bool &status_change)
                 break;
             }
 
-            if (ISA_HAS_DELAY_SLOT && pcOffset == 0) {
-                // Walk past any annulled delay slot instructions.
-                Addr pcAddr = thisPC.instAddr() & BaseCPU::PCMask;
-                while (fetchAddr != pcAddr && blkOffset < numInsts) {
-                    blkOffset++;
-                    fetchAddr += instSize;
-                }
-                if (blkOffset >= numInsts)
-                    break;
-            }
-
             MachInst inst = TheISA::gtoh(cacheInsts[blkOffset]);
             decoder[tid]->moreBytes(thisPC, fetchAddr, inst);