Another typo

diff --git a/techlibs/xilinx/abc_ff.v b/techlibs/xilinx/abc_ff.v
index 91cfbc4c410cfaf31dfc49086e6f6b280679c48c..6f9011ef14afa36fc9699750cec2f4c3eb9b40ce 100644 (file)
--- a/techlibs/xilinx/abc_ff.v
+++ b/techlibs/xilinx/abc_ff.v
@@ -94,7 +94,7 @@ module FDPE (output reg Q, input C, CE, D, PRE);
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_PRE_INVERTED = 1'b0;
   wire \$nextQ , \$currQ ;
-  \$__ABC_FDCE #(
+  \$__ABC_FDPE #(
     .INIT(|0),
     .IS_C_INVERTED(IS_C_INVERTED),
     .IS_D_INVERTED(IS_D_INVERTED),