- Revert to a single crt0 (avoid ctr/xip variants).
- Add otional DMA bus for Cache Coherency on CPU(s) with DMA/Cache Coherency interface.
- Add AXI-Lite bus standard support.
+ - Add VexRiscv SMP CPU support.
[> API changes/Deprecation
--------------------------
from litex.soc.interconnect.csr import *
from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV32
-from litedram.common import LiteDRAMNativePort
-
import os
-import os.path
CPU_VARIANTS = {
)
]
+ from litedram.common import LiteDRAMNativePort
if "mp" in variant:
ncpus = int(variant[-2]) # FIXME
for n in range(ncpus):
("pythondata-cpu-picorv32", ("https://github.com/litex-hub/", False, True, None)),
("pythondata-cpu-serv", ("https://github.com/litex-hub/", False, True, None)),
("pythondata-cpu-vexriscv", ("https://github.com/litex-hub/", False, True, None)),
- ("pythondata-cpu-vexriscv_smp",("https://github.com/litex-hub/", True, True, None)),
+ ("pythondata-cpu-vexriscv-smp",("https://github.com/litex-hub/", True, True, None)),
("pythondata-cpu-rocket", ("https://github.com/litex-hub/", False, True, None)),
("pythondata-cpu-minerva", ("https://github.com/litex-hub/", False, True, None)),
("pythondata-cpu-microwatt", ("https://github.com/litex-hub/", False, True, 0xba76652)),