arch-arm: Add used attribute to pauth_helpers asserts

Adding M5_VAR_USED attribute to variables in pauth_helpers so that
gem5.fast builds.

Change-Id: I45dd70ea2e921f7ce68ea52147abdd40da99f37e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25364
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

diff --git a/src/arch/arm/pauth_helpers.cc b/src/arch/arm/pauth_helpers.cc
index 892a414d6945bedbc42c73e3b893ff3dbb054555..1c83d77b8c2bda0a8a053f013a62dea3aa5cd4aa 100644 (file)
--- a/src/arch/arm/pauth_helpers.cc
+++ b/src/arch/arm/pauth_helpers.cc
@@ -113,9 +113,8 @@ ArmISA::calculateBottomPACBit(ThreadContext* tc, ExceptionLevel el,
 Fault
 ArmISA::trapPACUse(ThreadContext *tc, ExceptionLevel target_el)
 {
-    ExceptionLevel curr_el = currEL(tc);
     assert(ArmSystem::haveEL(tc, target_el) &&
-           target_el != EL0 && (target_el >= curr_el));
+           target_el != EL0 && (target_el >= currEL(tc)));
 
     switch (target_el) {
        case EL2:
@@ -149,7 +148,7 @@ ArmISA::addPAC (ThreadContext* tc, ExceptionLevel el, uint64_t  ptr,
     if (upperAndLowerRange(tc, el)) {
         ExceptionLevel s1_el = s1TranslationRegime(tc, el);
         assert (s1_el == EL1 || s1_el == EL2);
-        if (s1TranslationRegime(tc, el) == EL1) {
+        if (s1_el == EL1) {
             // EL1 translation regime registers
             TCR tcr = tc->readMiscReg(MISCREG_TCR_EL1);
             if (data) {