fmv/mvlq/fsq

diff --git a/riscv/insns/fcvt_s_wu.h b/riscv/insns/fcvt_s_wu.h
index c1394c3fd04af3f078f9cd29d201a52c63e199e4..b3cade4c2d9cf6e3dd69379ebc112bfac904abd0 100644 (file)
--- a/riscv/insns/fcvt_s_wu.h
+++ b/riscv/insns/fcvt_s_wu.h
@@ -1,5 +1,5 @@
 require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(ui32_to_f32((uint32_t)RS1));
+WRITE_FRD(ui32_to_f32(sv_reg_uint32(RS1)));
 set_fp_exceptions;

diff --git a/riscv/insns/fld.h b/riscv/insns/fld.h
index 4dea1d47e92476ee8de3aec2119243c566d09ee9..c63fdd80498b612ffaadf16b7abcb1f7bdd4fff6 100644 (file)
--- a/riscv/insns/fld.h
+++ b/riscv/insns/fld.h
@@ -1,3 +1,3 @@
 require_extension('D');
 require_fp;
-WRITE_FRD(f64(MMU.load_uint64(RS1 + insn.i_imm())));
+WRITE_FRD(f64(MMU.load_uint64(rv_add(RS1, insn.i_imm()))));

diff --git a/riscv/insns/flq.h b/riscv/insns/flq.h
index 81d225cd2223a0c583f4a20c3104409e75b1a9ea..0e371ef4399de4426837426f524c6d02f98330f1 100644 (file)
--- a/riscv/insns/flq.h
+++ b/riscv/insns/flq.h
@@ -1,3 +1,3 @@
 require_extension('Q');
 require_fp;
-WRITE_FRD(MMU.load_float128(RS1 + insn.i_imm()));
+WRITE_FRD(MMU.load_float128(rv_add(RS1, insn.i_imm())));

diff --git a/riscv/insns/flw.h b/riscv/insns/flw.h
index 61297544405cb65b65da17122e98247fccafa2ff..301b9b2c0706ed7e1e562cdd0eb185e377743205 100644 (file)
--- a/riscv/insns/flw.h
+++ b/riscv/insns/flw.h
@@ -1,3 +1,3 @@
 require_extension('F');
 require_fp;
-WRITE_FRD(f32(MMU.load_uint32(RS1 + insn.i_imm())));
+WRITE_FRD(f32(MMU.load_uint32(rv_add(RS1, insn.i_imm()))));

diff --git a/riscv/insns/fmv_x_w.h b/riscv/insns/fmv_x_w.h
index 6754f8693f329bc16faed03f54c4481dbb305a56..ca23310b3a5f195220f90a09368c5aa821d9a913 100644 (file)
--- a/riscv/insns/fmv_x_w.h
+++ b/riscv/insns/fmv_x_w.h
@@ -1,3 +1,3 @@
 require_extension('F');
 require_fp;
-WRITE_RD(sext32(FRS1.v[0]));
+WRITE_RD(sext32(sv_reg_t(FRS1.v[0])));

diff --git a/riscv/insns/fsd.h b/riscv/insns/fsd.h
index 38c702b7a01bccb72eeb623ee5a84f68f61db615..f1a76ab7a6b4291f00ec0209f65058b206396b5e 100644 (file)
--- a/riscv/insns/fsd.h
+++ b/riscv/insns/fsd.h
@@ -1,3 +1,3 @@
 require_extension('D');
 require_fp;
-MMU.store_uint64(RS1 + insn.s_imm(), FRS2.v[0]);
+MMU.store_uint64(rv_add(RS1, insn.s_imm()), FRS2.v[0]);

diff --git a/riscv/insns/fsq.h b/riscv/insns/fsq.h
index 610960e5998c1e8fe20ca0ca4b730174c41920ed..b3e9c08e320f67316a9fac3512eb607206f11329 100644 (file)
--- a/riscv/insns/fsq.h
+++ b/riscv/insns/fsq.h
@@ -1,3 +1,3 @@
 require_extension('Q');
 require_fp;
-MMU.store_float128(RS1 + insn.s_imm(), FRS2);
+MMU.store_float128(rv_add(RS1, insn.s_imm()), FRS2);

diff --git a/riscv/insns/fsw.h b/riscv/insns/fsw.h
index 8af51845f4a5306ef12cf2a703b16f15b6a0ce67..226e30e006793d03c60b3334bd5fc5477eaf567a 100644 (file)
--- a/riscv/insns/fsw.h
+++ b/riscv/insns/fsw.h
@@ -1,3 +1,3 @@
 require_extension('F');
 require_fp;
-MMU.store_uint32(RS1 + insn.s_imm(), FRS2.v[0]);
+MMU.store_uint32(rv_add(RS1, insn.s_imm()), FRS2.v[0]);