cores/uart/RS232PHYTX: fix startbit duration by pre-loading phase_accumulator_tx...

diff --git a/litex/soc/cores/uart.py b/litex/soc/cores/uart.py
index eafbe6c03254062e10a86850da6b08c05b73ede2..011fe5503e3f7e0e1609a28c06acf0400397b10d 100644 (file)
--- a/litex/soc/cores/uart.py
+++ b/litex/soc/cores/uart.py
@@ -99,7 +99,8 @@ class RS232PHYTX(Module):
             If(self.sink.valid & ~tx_busy & ~self.sink.ready,
                 tx_reg.eq(self.sink.data),
                 tx_bitcount.eq(0),
-                tx_busy.eq(1)
+                tx_busy.eq(1),
+                pads.tx.eq(0)
             ).Elif(uart_clk_txen & tx_busy,
                 tx_bitcount.eq(tx_bitcount + 1),
                 If(tx_bitcount == 8,
@@ -112,17 +113,13 @@ class RS232PHYTX(Module):
                     pads.tx.eq(tx_reg[0]),
                     tx_reg.eq(Cat(tx_reg[1:], 0))
                 )
-            ).Elif(tx_busy,
-                If(tx_bitcount == 0,
-                    pads.tx.eq(0)
-                )
             )
         ]
         self.sync += [
                 If(tx_busy,
                     Cat(phase_accumulator_tx, uart_clk_txen).eq(phase_accumulator_tx + tuning_word)
                 ).Else(
-                    Cat(phase_accumulator_tx, uart_clk_txen).eq(0)
+                    Cat(phase_accumulator_tx, uart_clk_txen).eq(tuning_word)
                 )
         ]