See <https://bugs.libre-soc.org/show_bug.cgi?id=230#c30>
-Note that some of these may be covered by [[remap]] which is described in [[sv/propagation]]
+Note that some of these may be covered by [[remap]].
# move to/from vec2/3/4
These are Scalar equivalents to VSX Pack and Unpack: v3.1
Book I Section 6.8 p278. Saturated variants do not need
adding because SVP64 overrides add Saturation already.
-half source width (word) variants would be helpful for
-the Scalar ISA.
+More detailed merging may be achieved with [[sv/bitmanip]]
+instructions.
| 0.5 |6.10|11.15|16..20|21..25|26.....30|31| name |
|-----|----|-----|------|------|---------|--|--------------|
-| 19 | RT | RC | RB/0 | RA/0 | XO[5:9] |Rc| mv.zip |
+| 19 | RTp| RC | RB/0 | RA/0 | XO[5:9] |Rc| mv.zip |
| 19 | RT | RC | RS/0 | RA/0 | XO[5:9] |Rc| mv.unzip |
these are specialist operations that zip or unzip to/from multiple regs to/from one vector including vec2/3/4. when SUBVL!=1 the vec2/3/4 is the contiguous unit that is copied (as if one register). different elwidths result in zero-extension or truncation except if saturation is enabled, where signed/unsigned may be applied as usual.