[pk,sim,xcc] get rid of at register, introduce tp register

diff --git a/riscv/insns/mfcr.h b/riscv/insns/mfcr.h
index 1d6b4d153857d665c3a74983a5baae9dab6d5ea1..de3c19dc34d2eaa33629a665748f9ee7facbc1f6 100644 (file)
--- a/riscv/insns/mfcr.h
+++ b/riscv/insns/mfcr.h
@@ -11,8 +11,7 @@ switch(insn.rtype.rs2)
     break;
 
   case 29:
-    val = tid;
-    break;
+    throw trap_illegal_instruction;
 
   default:
     val = -1;

diff --git a/riscv/insns/mtcr.h b/riscv/insns/mtcr.h
index ba55899743adcbfef52d38ce1b56a06555638361..df56ecd83a88da08e626330f232ff287972577c6 100644 (file)
--- a/riscv/insns/mtcr.h
+++ b/riscv/insns/mtcr.h
@@ -5,6 +5,5 @@ switch(insn.rtype.rs2)
     break;
 
   case 29:
-    tid = RS1;
-    break;
+    throw trap_illegal_instruction;
 }

diff --git a/riscv/processor.cc b/riscv/processor.cc
index a889f75ccc23f64cf1d1a5a29016ad5a31b011ce..684f95df930e65303e5a3080c48f4a87e16691da 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -19,7 +19,6 @@ processor_t::processor_t(sim_t* _sim, char* _mem, size_t _memsz)
   epc = 0;
   badvaddr = 0;
   cause = 0;
-  tid = 0;
   pcr_k0 = 0;
   pcr_k1 = 0;
   tohost = 0;

diff --git a/riscv/processor.h b/riscv/processor.h
index c1e4740094e071989da8cb94f6acf22385abc005..9ccfbb432558600578dc17ce1b1671909b6f42ba 100644 (file)
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -39,7 +39,6 @@ private:
   uint32_t interrupts_pending;
 
   // unprivileged control registers
-  uint32_t tid;
   uint32_t fsr;
 
   // 32-bit or 64-bit mode (redundant with sr)