ARM: Add back in spots for Rhi and Rlo, and use a named constant for LR.

diff --git a/src/arch/arm/intregs.hh b/src/arch/arm/intregs.hh
index 191965c5579511808d5611cc45fb6ba79bd99074..78ad39ee2aa69664b5d662fd748a55ae154a3692 100644 (file)
--- a/src/arch/arm/intregs.hh
+++ b/src/arch/arm/intregs.hh
@@ -102,6 +102,8 @@ enum IntRegIndex
 
     INTREG_ZERO, // Dummy zero reg since there has to be one.
     INTREG_UREG0,
+    INTREG_RHI,
+    INTREG_RLO,
 
     NUM_INTREGS,
     NUM_ARCH_INTREGS = INTREG_PC + 1,

diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index a4c404bd55d25629e346fb67df03327d790c220f..4ac6790e54d6db4ea66f59311cf3d7c00df66768 100644 (file)
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -63,9 +63,9 @@ def operands {{
     'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4, maybePCRead, maybePCWrite),
     'Rde': ('IntReg', 'uw', '(RD | 1)', 'IsInteger', 5, maybePCRead, maybePCWrite),
 
-    'Rhi': ('IntReg', 'uw', '18', 'IsInteger', 7),
-    'Rlo': ('IntReg', 'uw', '19', 'IsInteger', 8),
-    'LR': ('IntReg', 'uw', '14', 'IsInteger', 9),
+    'Rhi': ('IntReg', 'uw', 'INTREG_RHI', 'IsInteger', 7),
+    'Rlo': ('IntReg', 'uw', 'INTREG_RLO', 'IsInteger', 8),
+    'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 9),
 
     #Register fields for microops
     'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 11, maybePCRead, maybePCWrite),