Revert "write_xaiger: use sigmap bits more consistently"

This reverts commit 6c340112fee1bb8989cbd41923aaa627d77d5110.

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index cff3183c1588878a3d09aec7b1a3c902e53d30a0..c080cca4dd17d6d41ec2da1b569e6b5144641e6d 100644 (file)
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -294,7 +294,7 @@ struct XAigerWriter
                                                        output_bits.insert(b);
 
                                                        if (!cell_known)
-                                                               inout_bits.insert(I);
+                                                               inout_bits.insert(b);
                                                }
                                        }
                                }
@@ -315,7 +315,7 @@ struct XAigerWriter
                                                SigBit O = sigmap(b);
                                                if (O != b)
                                                        alias_map[O] = b;
-                                               input_bits.insert(O);
+                                               input_bits.insert(b);
 
                                                if (arrival)
                                                        arrival_times[b] = arrival;
@@ -542,8 +542,9 @@ struct XAigerWriter
                                undriven_bits.erase(bit);
                        }
 
-               // For inout ports, or keep-ed wires, which end up being both a PI and a
-               // a PO then replace the PO with a new wire with the $inout.out suffix
+               // For inout ports, or keep-ed wires, then create a new wire with an
+               // $inout.out suffix, make it a PO driven by the existing inout, and
+               // inherit existing inout's drivers
                for (auto bit : inout_bits) {
                        RTLIL::Wire *wire = bit.wire;
                        RTLIL::IdString wire_name = stringf("$%s$inout.out", wire->name.c_str());