move integrated BIOS code to gensoc

diff --git a/misoclib/gensoc/__init__.py b/misoclib/gensoc/__init__.py
index af09dfb9c3c75b2f0b3c5c6882c7ee572b6e174c..d89073da2e763319fea7b4f806a78e88de4677d5 100644 (file)
--- a/misoclib/gensoc/__init__.py
+++ b/misoclib/gensoc/__init__.py
@@ -69,13 +69,13 @@ class GenSoC(Module):
                        "jtag_tap_spartan6.v", "lm32_itlb.v", "lm32_dtlb.v")
                platform.add_sources(os.path.join("verilog", "lm32"), "lm32_config.v")
 
-       def register_rom(self, rom_wb_if):
+       def register_rom(self, rom_wb_if, bios_size=0x8000):
                if self._rom_registered:
                        raise FinalizeError
                self._rom_registered = True
 
                self.add_wb_slave(lambda a: a[26:29] == 0, rom_wb_if)
-               self.add_cpu_memory_region("rom", self.cpu_reset_address, 0x8000) # 32KB for BIOS
+               self.add_cpu_memory_region("rom", self.cpu_reset_address, bios_size)
 
        def add_wb_master(self, wbm):
                if self.finalized:
@@ -114,6 +114,14 @@ class GenSoC(Module):
                        t += clk_period_ns/2
                return ceil(t/clk_period_ns)
 
+class IntegratedBIOS:
+       def __init__(self, bios_size=0x8000):
+               self.submodules.rom = wishbone.SRAM(bios_size)
+               self.register_rom(self.rom.bus, bios_size)
+
+       def init_bios_memory(self, data):
+               self.rom.mem.init = data
+
 class SDRAMSoC(GenSoC):
        csr_map = {
                "dfii":                                 6,

diff --git a/targets/simple.py b/targets/simple.py
index 01e976c6fbfeda656cec7c152edf5d6d172e8865..7cefa6d96f9fbc4e151a7b10df0c1474f940c9c1 100644 (file)
--- a/targets/simple.py
+++ b/targets/simple.py
@@ -1,25 +1,19 @@
 from migen.fhdl.std import *
-from migen.bus import wishbone
 
-from misoclib.gensoc import GenSoC
+from misoclib.gensoc import GenSoC, IntegratedBIOS
 
-class SimpleSoC(GenSoC):
+class SimpleSoC(GenSoC, IntegratedBIOS):
        def __init__(self, platform):
                GenSoC.__init__(self, platform,
                        clk_freq=32*1000000,
                        cpu_reset_address=0,
                        sram_size=4096)
+               IntegratedBIOS.__init__(self)
 
                # We can't use reset_less as LM32 does require a reset signal
                self.clock_domains.cd_sys = ClockDomain()
                self.comb += self.cd_sys.clk.eq(platform.request("clk32"))
                self.specials += Instance("FD", p_INIT=1, i_D=0, o_Q=self.cd_sys.rst, i_C=ClockSignal())
 
-               self.submodules.rom = wishbone.SRAM(32768)
-               self.register_rom(self.rom.bus)
-
-       def init_bios_memory(self, data):
-               self.rom.mem.init = data
-
 def get_default_subtarget(platform):
        return SimpleSoC