(no commit message)

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index ee1344924296acd774abd8d9293b37af66e88f98..3ee7c38edefcd1bc9dc3b28751ade2927d6c758b 100644 (file)
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -721,14 +721,17 @@ for i in 0 to VL-1:
 
 The reason why should be clear from this being a Vector loop:
 unconditional destruction of LR when LK=1 makes `bclrl`
-ineffective.  However if the change to LR only occurs if
+ineffective, because the intention going into the loop is
+that the branch should be to the copy of LR set at the *start*
+of the loop, not half way through it.
+However if the change to LR only occurs if
 the branch is taken then it becomes a useful instruction.
 
 The following pseudocode should **not** be implemented because
 it violates the fundamental principle of SVP64 which is that
 SVP64 looping is a thin wrapper around Scalar Instructions.
 The pseducode below is more an actual Vector ISA Branch and
-as such is not aporopriate:
+as such is not at all appropriate:
 
 ```
 for i in 0 to VL-1: