(no commit message)

diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn
index 3fcb519eb083793eccca3dbe47985c068f473ea5..7317a37eae327545596a2dd16f8a34df1bfd3078 100644 (file)
--- a/openpower/sv/ldst.mdwn
+++ b/openpower/sv/ldst.mdwn
@@ -13,7 +13,7 @@ Links:
 Vectorisation of Load and Store requires creation, from scalar operations,
 a number of different modes:
 
-* fixed stride (contiguous sequence with no gaps)
+* fixed stride (contiguous sequence with no gaps) aka "unit" stride
 * element strided (sequential but regularly offset, with gaps)
 * vector indexed (vector of base addresses and vector of offsets)
 * fail-first on the same (where it makes sense to do so)
@@ -284,7 +284,7 @@ LD/ST, will give that same capability, with far more flexibility.
 this section covers assembly notation for the immediate and indexed LD/ST.
 the summary is that in immediate mode for LD it is not clear that if the 
 destination register is Vectorised `RT.v` but the source `imm(RA)` is scalar
-the memory being read is *still a vector load*.
+the memory being read is *still a vector load*, known as "unit or element strides".
 
 This anomaly is made clear with the following notation: