Added tests of automatic parallelisation.

diff --git a/gas/testsuite/.Sanitize b/gas/testsuite/.Sanitize
index 75f6d79f1dfd5e4ff581a135d529676f71db5e5e..17290d3293684ae03f761515524ee6133a0e4f46 100644 (file)
--- a/gas/testsuite/.Sanitize
+++ b/gas/testsuite/.Sanitize
@@ -240,4 +240,37 @@ else
        done
 fi
 
+m32rx_files="ChangeLog"
+if ( echo $* | grep keep\-m32rx > /dev/null ) ; then
+       for i in $m32rx_files ; do
+               if test ! -d $i && (grep sanitize-m32rx $i > /dev/null) ; then
+                       if [ -n "${verbose}" ] ; then
+                               echo Keeping m32rx stuff in $i
+                       fi
+               fi
+       done
+else
+       for i in $m32rx_files ; do
+               if test ! -d $i && (grep sanitize-m32rx $i > /dev/null) ; then
+                       if [ -n "${verbose}" ] ; then
+                               echo Removing traces of \"m32rx\" from $i...
+                       fi
+                       cp $i new
+                       sed '/start\-sanitize\-m32rx/,/end-\sanitize\-m32rx/d' < $i > new
+                       if [ -n "${safe}" -a ! -f .Recover/$i ] ; then
+                               if [ -n "${verbose}" ] ; then
+                                       echo Caching $i in .Recover...
+                               fi
+                               mv $i .Recover
+                       fi
+                       mv new $i
+               fi
+       done
+fi
+
+for i in * ; do
+       if test ! -d $i && (grep sanitize $i > /dev/null) ; then
+               echo '***' Some mentions of Sanitize are still left in $i! 1>&2
+       fi
+done
 # End of file.

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 21bbcaa896b83c1f0454ee0369f214425ab38b9b..22f527a1cd28e4ddc142a4fa09f9800e9000a3d2 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,16 @@
+Thu Jan 22 17:29:07 1998  Nick Clifton  <nickc@cygnus.com>
+
+       * gas/m32r/high-1.d: Add hash prefix to constants.
+
+       * gas/m32r/allinsn.s: Add hash prefix to some constants.
+       * gas/m32r/allinsn.d: Add hash prefix to constants.
+start-sanitize-m32rx
+       * gas/m32r/m32rx.s: Add tests for automatic parallelisation.
+       * gas/m32r/m32rx.d: Add results of automatic parallelisation.
+       * gas/m32r/relax-1.d: Add results of automatic parallelisation.
+       * gas/m32r/uppercase.d: Add results of automatic parallelisation.
+end-sanitize-m32rx
+
 Wed Jan 21 21:24:08 1998  Manfred Hollstein  <manfred@s-direktnet.de>
 
        * gas/m88k/init.d: Fix hexadecimal offsets.
@@ -6,8 +19,10 @@ Wed Jan 14 17:49:22 1998  Nick Clifton  <nickc@cygnus.com>
 
        * gas/m32r/uppercase.d: Fix white space matching.
        * gas/m32r/relax-1.d: Fix white space matching.
+start-sanitize-m32rx   
        * gas/m32r/m32rx.d: Add expected results.
        * gas/m32r/m32rx.s: Correct typos in test cases.
+end-sanitize-m32rx     
 
 Wed Jan 14 15:44:32 1998  Jeffrey A Law  (law@cygnus.com)
 

diff --git a/gas/testsuite/gas/m32r/high-1.d b/gas/testsuite/gas/m32r/high-1.d
new file mode 100644 (file)
index 0000000..656c39c
--- /dev/null
+++ b/gas/testsuite/gas/m32r/high-1.d
@@ -0,0 +1,19 @@
+#as:
+#objdump: -dr
+#name: high-1
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0* <foo>:
+ *0:   d4 c0 00 01     seth r4,#0x1
+[      ]*0: R_M32R_HI16_ULO    .text
+ *4:   84 e4 00 00     or3 r4,r4,#0x0
+[      ]*4: R_M32R_LO16        .text
+ *8:   d4 c0 12 34     seth r4,#0x1234
+ *c:   84 e4 87 65     or3 r4,r4,#0x8765
+ *10:  d4 c0 12 35     seth r4,#0x1235
+ *14:  84 e4 87 65     or3 r4,r4,#0x8765
+ *18:  d4 c0 87 65     seth r4,#0x8765
+ *1c:  84 e4 43 21     or3 r4,r4,#0x4321

diff --git a/gas/testsuite/gas/m32r/m32rx.d b/gas/testsuite/gas/m32r/m32rx.d
index 1ea7671b9960b1e9e3cba28019b7d3b6a728aba9..4fbd5e95dbf55be3d41cf5cbef08d4729eaf7793 100644 (file)
--- a/gas/testsuite/gas/m32r/m32rx.d
+++ b/gas/testsuite/gas/m32r/m32rx.d
@@ -82,218 +82,177 @@ Disassembly of section .text:
   60:  50 80 f0 00     rach || nop
 
 00000064 <bc__add>:
-  64:  7c 00 8d ad     bc 64 <bc__add> || add fp,fp
-  68:  7c e6           bc 0 <bcl>
-  6a:  0d ad           add fp,fp
+  64:  7c e7 8d ad     bc 0 <bcl> || add fp,fp
+  68:  7c e6 0d ad     bc 0 <bcl> -> add fp,fp
 
 0000006c <bcl__addi>:
-  6c:  78 00 cd 4d     bcl 6c <bcl__addi> || addi fp,77
-  70:  4d 4d           addi fp,77
-  72:  78 e4           bcl 2 <bcl\+0x2>
+  6c:  78 e5 cd 4d     bcl 0 <bcl> || addi fp,#77
+  70:  78 e4 cd 4d     bcl 0 <bcl> || addi fp,#77
 
 00000074 <bl__addv>:
-  74:  7e 00 8d 8d     bl 74 <bl__addv> || addv fp,fp
-  78:  0d 8d           addv fp,fp
-  7a:  7e e2           bl 2 <bcl\+0x2>
+  74:  7e e3 8d 8d     bl 0 <bcl> || addv fp,fp
+  78:  7e e2 8d 8d     bl 0 <bcl> || addv fp,fp
 
 0000007c <bnc__addx>:
-  7c:  7d 00 8d 9d     bnc 7c <bnc__addx> || addx fp,fp
-  80:  7d e0           bnc 0 <bcl>
-  82:  0d 9d           addx fp,fp
+  7c:  7d e1 8d 9d     bnc 0 <bnc> || addx fp,fp
+  80:  7d e0 0d 9d     bnc 0 <bcl> -> addx fp,fp
 
 00000084 <bncl__and>:
-  84:  79 00 8d cd     bncl 84 <bncl__and> || and fp,fp
-  88:  79 de           bncl 0 <bcl>
-  8a:  0d cd           and fp,fp
+  84:  79 df 8d cd     bncl 0 <bcl> || and fp,fp
+  88:  79 de 0d cd     bncl 0 <bcl> -> and fp,fp
 
 0000008c <bra__cmp>:
-  8c:  7f 00 8d 4d     bra 8c <bra__cmp> || cmp fp,fp
-  90:  0d 4d           cmp fp,fp
-  92:  7f dc           bra 2 <bcl\+0x2>
+  8c:  7f dd 8d 4d     bra 0 <bcl> || cmp fp,fp
+  90:  7f dc 8d 4d     bra 0 <bcl> || cmp fp,fp
 
 00000094 <jl__cmpeq>:
   94:  1e cd 8d 6d     jl fp || cmpeq fp,fp
-  98:  0d 6d           cmpeq fp,fp
-  9a:  1e cd           jl fp
+  98:  1e cd 8d 6d     jl fp || cmpeq fp,fp
 
 0000009c <jmp__cmpu>:
   9c:  1f cd 8d 5d     jmp fp || cmpu fp,fp
-  a0:  0d 5d           cmpu fp,fp
-  a2:  1f cd           jmp fp
+  a0:  1f cd 8d 5d     jmp fp || cmpu fp,fp
 
 000000a4 <ld__cmpz>:
   a4:  2d cd 80 71     ld fp,@fp || cmpz r1
-  a8:  00 71           cmpz r1
-  aa:  2d cd           ld fp,@fp
+  a8:  2d cd 80 71     ld fp,@fp || cmpz r1
 
 000000ac <ld__ldi>:
-  ac:  2d e1 e2 4d     ld fp,@r1\+ || ldi r2,77
-  b0:  2d e1           ld fp,@r1\+
-  b2:  62 4d           ldi r2,77
+  ac:  2d e1 e2 4d     ld fp,@r1\+ || ldi r2,#77
+  b0:  2d e1 e2 4d     ld fp,@r1\+ || ldi r2,#77
 
 000000b4 <ldb__mv>:
   b4:  2d 8d 92 8d     ldb fp,@fp || mv r2,fp
-  b8:  2d 8d           ldb fp,@fp
-  ba:  12 8d           mv r2,fp
+  b8:  2d 8d 12 8d     ldb fp,@fp -> mv r2,fp
 
 000000bc <ldh__neg>:
   bc:  2d ad 82 3d     ldh fp,@fp || neg r2,fp
-  c0:  2d ad           ldh fp,@fp
-  c2:  02 3d           neg r2,fp
+  c0:  2d ad 02 3d     ldh fp,@fp -> neg r2,fp
 
 000000c4 <ldub__nop>:
   c4:  2d 9d f0 00     ldub fp,@fp || nop
-  c8:  2d 9d           ldub fp,@fp
-  ca:  70 00           nop
+  c8:  2d 9d f0 00     ldub fp,@fp || nop
 
 000000cc <lduh__not>:
   cc:  2d bd 82 bd     lduh fp,@fp || not r2,fp
-  d0:  2d bd           lduh fp,@fp
-  d2:  02 bd           not r2,fp
+  d0:  2d bd 02 bd     lduh fp,@fp -> not r2,fp
 
 000000d4 <lock__or>:
   d4:  2d dd 82 ed     lock fp,@fp || or r2,fp
-  d8:  2d dd           lock fp,@fp
-  da:  02 ed           or r2,fp
+  d8:  2d dd 02 ed     lock fp,@fp -> or r2,fp
 
 000000dc <mvfc__sub>:
   dc:  1d 91 82 2d     mvfc fp,cbr || sub r2,fp
-  e0:  1d 91           mvfc fp,cbr
-  e2:  02 2d           sub r2,fp
+  e0:  1d 91 02 2d     mvfc fp,cbr -> sub r2,fp
 
 000000e4 <mvtc__subv>:
   e4:  10 ad 82 0d     mvtc fp,psw || subv r2,fp
-  e8:  10 ad           mvtc fp,psw
-  ea:  02 0d           subv r2,fp
+  e8:  10 ad 82 0d     mvtc fp,psw || subv r2,fp
 
 000000ec <rte__subx>:
   ec:  10 d6 82 1d     rte || subx r2,fp
-  f0:  10 d6           rte
-  f2:  02 1d           subx r2,fp
+  f0:  10 d6 02 1d     rte -> subx r2,fp
 
 000000f4 <sll__xor>:
   f4:  1d 41 82 dd     sll fp,r1 || xor r2,fp
-  f8:  1d 41           sll fp,r1
-  fa:  02 dd           xor r2,fp
+  f8:  1d 41 02 dd     sll fp,r1 -> xor r2,fp
 
 000000fc <slli__machi>:
-  fc:  5d 56 b2 4d     slli fp,0x16 || machi r2,fp
- 100:  5d 56           slli fp,0x16
- 102:  32 4d           machi r2,fp
+  fc:  5d 56 b2 4d     slli fp,#0x16 || machi r2,fp
+ 100:  5d 56 32 4d     slli fp,#0x16 -> machi r2,fp
 
 00000104 <sra__machl1>:
  104:  1d 2d d2 cd     sra fp,fp || machl1 r2,fp
- 108:  1d 2d           sra fp,fp
- 10a:  52 cd           machl1 r2,fp
+ 108:  1d 2d 52 cd     sra fp,fp -> machl1 r2,fp
 
 0000010c <srai__maclo>:
- 10c:  5d 36 b2 5d     srai fp,0x16 || maclo r2,fp
- 110:  5d 36           srai fp,0x16
- 112:  32 5d           maclo r2,fp
+ 10c:  5d 36 b2 5d     srai fp,#0x16 || maclo r2,fp
+ 110:  5d 36 32 5d     srai fp,#0x16 -> maclo r2,fp
 
 00000114 <srl__macwhi>:
  114:  1d 0d b2 6d     srl fp,fp || macwhi r2,fp
- 118:  1d 0d           srl fp,fp
- 11a:  32 6d           macwhi r2,fp
+ 118:  1d 0d 32 6d     srl fp,fp -> macwhi r2,fp
 
 0000011c <srli__macwlo>:
- 11c:  5d 16 b2 7d     srli fp,0x16 || macwlo r2,fp
- 120:  5d 16           srli fp,0x16
- 122:  32 7d           macwlo r2,fp
+ 11c:  5d 16 b2 7d     srli fp,#0x16 || macwlo r2,fp
+ 120:  5d 16 32 7d     srli fp,#0x16 -> macwlo r2,fp
 
 00000124 <st__macwu1>:
  124:  2d 4d d2 bd     st fp,@fp || macwu1 r2,fp
- 128:  2d 4d           st fp,@fp
- 12a:  52 bd           macwu1 r2,fp
+ 128:  2d 4d d2 bd     st fp,@fp || macwu1 r2,fp
 
 0000012c <st__msblo>:
- 12c:  2d 6d d2 dd     st fp,@\+fp || msblo r2,fp
- 130:  2d 6d           st fp,@\+fp
- 132:  52 dd           msblo r2,fp
+ 12c:  2d 6d d2 dd     st fp,@+fp || msblo r2,fp
+ 130:  2d 6d d2 dd     st fp,@+fp || msblo r2,fp
 
 00000134 <st__mul>:
  134:  2d 7d 92 6d     st fp,@-fp || mul r2,fp
- 138:  2d 7d           st fp,@-fp
- 13a:  12 6d           mul r2,fp
+ 138:  2d 7d 92 6d     st fp,@-fp || mul r2,fp
 
 0000013c <stb__mulhi>:
  13c:  2d 0d b2 0d     stb fp,@fp || mulhi r2,fp
- 140:  2d 0d           stb fp,@fp
- 142:  32 0d           mulhi r2,fp
+ 140:  2d 0d b2 0d     stb fp,@fp || mulhi r2,fp
 
 00000144 <sth__mullo>:
  144:  2d 2d b2 1d     sth fp,@fp || mullo r2,fp
- 148:  2d 2d           sth fp,@fp
- 14a:  32 1d           mullo r2,fp
+ 148:  2d 2d b2 1d     sth fp,@fp || mullo r2,fp
 
 0000014c <trap__mulwhi>:
- 14c:  10 f2 b2 2d     trap 0x2 || mulwhi r2,fp
- 150:  10 f2 f0 00     trap 0x2 || nop
+ 14c:  10 f2 b2 2d     trap #0x2 || mulwhi r2,fp
+ 150:  10 f2 f0 00     trap #0x2 || nop
  154:  32 2d f0 00     mulwhi r2,fp || nop
 
 00000158 <unlock__mulwlo>:
  158:  2d 5d b2 3d     unlock fp,@fp || mulwlo r2,fp
- 15c:  2d 5d           unlock fp,@fp
- 15e:  32 3d           mulwlo r2,fp
+ 15c:  2d 5d b2 3d     unlock fp,@fp || mulwlo r2,fp
 
 00000160 <add__mulwu1>:
  160:  0d ad d2 ad     add fp,fp || mulwu1 r2,fp
- 164:  0d ad           add fp,fp
- 166:  52 ad           mulwu1 r2,fp
+ 164:  0d ad 52 ad     add fp,fp -> mulwu1 r2,fp
 
 00000168 <addi__mvfachi>:
- 168:  4d 4d d2 f0     addi fp,77 || mvfachi r2
- 16c:  4d 4d           addi fp,77
- 16e:  52 f0           mvfachi r2
+ 168:  4d 4d d2 f0     addi fp,#77 || mvfachi r2
+ 16c:  4d 4d d2 f0     addi fp,#77 || mvfachi r2
 
 00000170 <addv__mvfaclo>:
- 170:  0d 8d d2 f1     addv fp,fp || mvfaclo r2
- 174:  0d 8d           addv fp,fp
- 176:  52 f1           mvfaclo r2
+ 170:  0d 8d d2 f5     addv fp,fp || mvfaclo r2,a1
+ 174:  0d 8d d2 f5     addv fp,fp || mvfaclo r2,a1
 
 00000178 <addx__mvfacmi>:
  178:  0d 9d d2 f2     addx fp,fp || mvfacmi r2
- 17c:  0d 9d           addx fp,fp
- 17e:  52 f2           mvfacmi r2
+ 17c:  0d 9d d2 f2     addx fp,fp || mvfacmi r2
 
 00000180 <and__mvtachi>:
  180:  0d cd d2 70     and fp,fp || mvtachi r2
- 184:  0d cd           and fp,fp
- 186:  52 70           mvtachi r2
+ 184:  0d cd d2 70     and fp,fp || mvtachi r2
 
 00000188 <cmp__mvtaclo>:
  188:  0d 4d d2 71     cmp fp,fp || mvtaclo r2
- 18c:  0d 4d           cmp fp,fp
- 18e:  52 71           mvtaclo r2
+ 18c:  0d 4d d2 71     cmp fp,fp || mvtaclo r2
 
 00000190 <cmpeq__rac>:
- 190:  0d 6d d0 90     cmpeq fp,fp || rac
- 194:  0d 6d           cmpeq fp,fp
- 196:  50 90           rac
+ 190:  0d 6d d0 94     cmpeq fp,fp || rac a1
+ 194:  0d 6d d0 94     cmpeq fp,fp || rac a1
 
 00000198 <cmpu__rach>:
  198:  0d 5d d0 80     cmpu fp,fp || rach
- 19c:  0d 5d           cmpu fp,fp
- 19e:  50 80           rach
+ 19c:  0d 5d d0 80     cmpu fp,fp || rach
 
 000001a0 <cmpz__sadd>:
  1a0:  00 7d d0 e4     cmpz fp || sadd
- 1a4:  00 7d           cmpz fp
- 1a6:  50 e4           sadd
+ 1a4:  00 7d d0 e4     cmpz fp || sadd
 
 000001a8 <sc>:
- 1a8:  74 01           sc
- 1aa:  50 e4           sadd
+ 1a8:  74 01 d0 e4     sc || sadd
 
 000001ac <snc>:
- 1ac:  75 01           snc
- 1ae:  50 e4           sadd
+ 1ac:  75 01 d0 e4     snc || sadd
 
 000001b0 <jc>:
  1b0:  1c cd f0 00     jc fp || nop
 
 000001b4 <jnc>:
- 1b4:  1c cd f0 00     jc fp || nop
+ 1b4:  1d cd f0 00     *unknown* || nop
 
 000001b8 <pcmpbz>:
  1b8:  03 7d f0 00     pcmpbz fp || nop
@@ -306,23 +265,57 @@ Disassembly of section .text:
 
 000001c4 <jc__pcmpbz>:
  1c4:  1c cd 83 7d     jc fp || pcmpbz fp
- 1c8:  1c cd           jc fp
- 1ca:  03 7d           pcmpbz fp
+ 1c8:  1c cd 03 7d     jc fp -> pcmpbz fp
 
 000001cc <jnc__ldi>:
- 1cc:  1c cd ed 4d     jc fp || ldi fp,77
- 1d0:  1c cd           jc fp
- 1d2:  6d 4d           ldi fp,77
+ 1cc:  1d cd ed 4d     \*unknown\* || ldi fp,#77
+ 1d0:  1d cd 6d 4d     \*unknown\* -> ldi fp,#77
 
 000001d4 <sc__mv>:
  1d4:  74 01 9d 82     sc || mv fp,r2
- 1d8:  74 01           sc
- 1da:  1d 82           mv fp,r2
+ 1d8:  74 01 9d 82     sc || mv fp,r2
 
 000001dc <snc__neg>:
  1dc:  75 01 8d 32     snc || neg fp,r2
- 1e0:  75 01           snc
- 1e2:  0d32            neg fp,r2
+ 1e0:  75 01 8d 32     snc || neg fp,r2
+
+000001e4 <nop__sadd>:
+ 1e4:  70 00 d0 e4     nop || sadd
+
+000001e8 <sadd__nop>:
+ 1e8:  70 00 d0 e4     nop || sadd
+
+000001ec <sadd__nop_reverse>:
+ 1ec:  70 00 d0 e4     nop || sadd
+
+000001f0 <add__not>:
+ 1f0:  00 a1 83 b5     add r0,r1 || not r3,r5
+
+000001f4 <add__not_dest_clash>:
+ 1f4:  03 a4 03 b5     add r3,r4 -> not r3,r5
+
+000001f8 <add__not__src_clash>:
+ 1f8:  03 a4 05 b3     add r3,r4 -> not r5,r3
+
+000001fc <add__not__no_clash>:
+ 1fc:  03 a4 84 b5     add r3,r4 || not r4,r5
+
+00000200 <mul__sra>:
+ 200:  13 24 91 62     sra r3,r4 || mul r1,r2
+
+00000204 <mul__sra__reverse_src_clash>:
+ 204:  13 24 91 63     sra r3,r4 || mul r1,r3
+
+00000208 <bc__add_>:
+ 208:  7c f7 01 a2     bc 1e4 <nop__sadd> -> add r1,r2
+
+0000020c <add__bc>:
+ 20c:  7c f6 83 a4     bc 1e4 <nop__sadd> || add r3,r4
+
+00000210 <bc__add__forced_parallel>:
+ 210:  7c f5 85 a6     bc 1e4 <nop__sadd> || add r5,r6
+
+00000214 <add__bc__forced_parallel>:
+ 214:  7c f4 87 a8     bc 1e4 <nop__sadd> || add r7,r8
 
-# To be completed once the instructions are in cgen.....
 

diff --git a/gas/testsuite/gas/m32r/m32rx.s b/gas/testsuite/gas/m32r/m32rx.s
index 70e4b2456ed5e932ff7bf3cd150583caa2b81225..df632a229c42d8a15db390782fc63a166fe4aa54 100644 (file)
--- a/gas/testsuite/gas/m32r/m32rx.s
+++ b/gas/testsuite/gas/m32r/m32rx.s
@@ -132,44 +132,44 @@ rach:
        .text
        .global bc__add
 bc__add:
-       bc branchpoint || add fp, fp
-       bc branchpoint
+       bc bcl || add fp, fp
+       bc bcl
        add fp, fp
 
        .text
        .global bcl__addi
 bcl__addi:     
-       bcl branchpoint || addi fp, #77
+       bcl bcl || addi fp, #77
        addi fp, #77
-       bcl branchpoint
+       bcl bcl
 
        .text
        .global bl__addv
 bl__addv:
-       bl branchpoint || addv fp, fp
+       bl bcl || addv fp, fp
        addv fp, fp
-       bl branchpoint
+       bl bcl
        
        .text
        .global bnc__addx
 bnc__addx:
-       bnc branchpoint || addx fp, fp
-       bnc branchpoint
+       bnc bcl || addx fp, fp
+       bnc bcl
        addx fp, fp
 
        .text
        .global bncl__and
 bncl__and:
-       bncl branchpoint || and fp, fp
-       bncl branchpoint
+       bncl bcl || and fp, fp
+       bncl bcl
        and fp, fp
 
        .text
        .global bra__cmp
 bra__cmp:
-       bra branchpoint || cmp fp, fp
+       bra bcl || cmp fp, fp
        cmp fp, fp
-       bra branchpoint
+       bra bcl
        
        .text
        .global jl__cmpeq
@@ -335,8 +335,8 @@ sth__mullo:
        .text
        .global trap__mulwhi
 trap__mulwhi:
-       trap 2 || mulwhi r2, fp
-       trap 2
+       trap #2 || mulwhi r2, fp
+       trap #2
        mulwhi r2, fp
 
        .text
@@ -480,7 +480,79 @@ snc__neg:
        snc 
        neg fp, r2
        
+# Test automatic and explicit parallelisation of instructions
+       .text
+       .global nop__sadd
+nop__sadd:
+label:         
+       nop
+       sadd
+
+       .text
+       .global sadd__nop
+sadd__nop:
+       sadd
+       nop
+
+       .text
+       .global sadd__nop_reverse
+sadd__nop_reverse:
+       sadd || nop
+
+       .text
+       .global add__not
+add__not:
+       add  r0, r1
+       not  r3, r5
+
+       .text
+       .global add__not__dest_clash
+add__not_dest_clash:
+       add  r3, r4
+       not  r3, r5
+
+       .text
+       .global add__not__src_clash
+add__not__src_clash:
+       add  r3, r4
+       not  r5, r3
+
+       .text
+       .global add__not__no_clash
+add__not__no_clash:
+       add  r3, r4
+       not  r4, r5
+
+       .text
+       .global mul__sra
+mul__sra:
+       mul  r1, r2
+       sra  r3, r4
        
+       .text
+       .global mul__sra__reverse_src_clash
+mul__sra__reverse_src_clash:
+       mul  r1, r3
+       sra  r3, r4
        
+       .text
+       .global bc__add_
+bc__add_:
+       bc label
+       add r1, r2
+
+       .text
+       .global add__bc
+add__bc:
+       add r3, r4
+       bc  label
 
-       
\ No newline at end of file
+       .text
+       .global bc__add__forced_parallel
+bc__add__forced_parallel:
+       bc label || add r5, r6
+
+       .text
+       .global add__bc__forced_parallel
+add__bc__forced_parallel:
+       add r7, r8 || bc label