soc/cores/flash/spi_flash: remove bitbanging comment (no longer supported)

diff --git a/litex/soc/cores/flash/spi_flash.py b/litex/soc/cores/flash/spi_flash.py
index 10190ae8a3053f7f7a5d3a0886f8d98c1f445ad7..14df3a4db7ef0d0aab204bb57b1a8e86e223ec36 100644 (file)
--- a/litex/soc/cores/flash/spi_flash.py
+++ b/litex/soc/cores/flash/spi_flash.py
@@ -31,7 +31,6 @@ class SpiFlashDualQuad(Module, AutoCSR):
         Simple SPI flash.
         Supports multi-bit pseudo-parallel reads (aka Dual or Quad I/O Fast
         Read). Only supports mode0 (cpol=0, cpha=0).
-        Optionally supports software bitbanging (for write, erase, or other commands).
         """
         self.bus = bus = wishbone.Interface()
         spi_width = len(pads.dq)
@@ -117,7 +116,6 @@ class SpiFlashSingle(Module, AutoCSR):
         """
         Simple SPI flash.
         Supports 1-bit reads. Only supports mode0 (cpol=0, cpha=0).
-        Optionally supports software bitbanging (for write, erase, or other commands).
         """
         self.bus = bus = wishbone.Interface()