Carry in/out box ordering now move to end, not swap with end

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 23132f10870fbad9413ed6851ebffef0c0fcc719..7cfe8272c45c3bdb632b94cdd4336aa3d99d9ad0 100644 (file)
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -309,38 +309,46 @@ struct XAigerWriter
 
                                if (box_module->attributes.count("\\abc_carry") && !abc_carry_modules.count(box_module)) {
                                        RTLIL::Wire* carry_in = nullptr, *carry_out = nullptr;
-                                       RTLIL::Wire* last_in = nullptr, *last_out = nullptr;
-                                       for (const auto &port_name : box_module->ports) {
-                                               RTLIL::Wire* w = box_module->wire(port_name);
+                                       auto &ports = box_module->ports;
+                                       for (auto it = ports.begin(); it != ports.end(); ) {
+                                               RTLIL::Wire* w = box_module->wire(*it);
                                                log_assert(w);
-                                               if (w->port_input) {
-                                                       if (w->attributes.count("\\abc_carry_in")) {
-                                                               log_assert(!carry_in);
-                                                               carry_in = w;
-                                                       }
-                                                       log_assert(!last_in || last_in->port_id < w->port_id);
-                                                       last_in = w;
+                                               if (w->port_input && w->attributes.count("\\abc_carry_in")) {
+                                                       if (carry_in)
+                                                               log_error("More than one port with attribute 'abc_carry_in' found in module '%s'\n", log_id(box_module));
+                                                       carry_in = w;
+                                                       it = ports.erase(it);
+                                                       continue;
                                                }
-                                               if (w->port_output) {
-                                                       if (w->attributes.count("\\abc_carry_out")) {
-                                                               log_assert(!carry_out);
-                                                               carry_out = w;
-                                                       }
-                                                       log_assert(!last_out || last_out->port_id < w->port_id);
-                                                       last_out = w;
+                                               if (w->port_output && w->attributes.count("\\abc_carry_out")) {
+                                                       if (carry_out)
+                                                               log_error("More than one port with attribute 'abc_carry_out' found in module '%s'\n", log_id(box_module));
+                                                       carry_out = w;
+                                                       it = ports.erase(it);
+                                                       continue;
                                                }
+                                               ++it;
                                        }
 
-                                       if (carry_in) {
-                                               log_assert(last_in);
-                                               std::swap(box_module->ports[carry_in->port_id-1], box_module->ports[last_in->port_id-1]);
-                                               std::swap(carry_in->port_id, last_in->port_id);
-                                       }
-                                       if (carry_out) {
-                                               log_assert(last_out);
-                                               std::swap(box_module->ports[carry_out->port_id-1], box_module->ports[last_out->port_id-1]);
-                                               std::swap(carry_out->port_id, last_out->port_id);
+                                       if (!carry_in)
+                                               log_error("Port with attribute 'abc_carry_in' not found in module '%s'\n", log_id(box_module));
+                                       if (!carry_out)
+                                               log_error("Port with attribute 'abc_carry_out' not found in module '%s'\n", log_id(box_module));
+
+                                       for (const auto port_name : ports) {
+                                               RTLIL::Wire* w = box_module->wire(port_name);
+                                               log_assert(w);
+                                               if (w->port_id > carry_in->port_id)
+                                                       --w->port_id;
+                                               if (w->port_id > carry_out->port_id)
+                                                       --w->port_id;
+                                               log_assert(w->port_input || w->port_output);
+                                               log_assert(ports[w->port_id-1] == w->name);
                                        }
+                                       ports.push_back(carry_in->name);
+                                       carry_in->port_id = ports.size();
+                                       ports.push_back(carry_out->name);
+                                       carry_out->port_id = ports.size();
                                }
 
                                // Fully pad all unused input connections of this box cell with S0

diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
index c9d80a333c2f9be5abcd443a1183756e05437c8a..0a6a6eaf0fa5b7160b20e58b88865841151b05b0 100644 (file)
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@ -12,17 +12,17 @@ MUXF8 2 1 3 1
 104 94 273
 
 # CARRY4 + CARRY4_[ABCD]X
-# Inputs: S0 S1 S2 S3 CYINIT DI0 DI1 DI2 DI3 CI
+# Inputs: CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3 CI
 # Outputs:  O0 O1 O2 O3 CO0 CO1 CO2 CO3
-#   (NB: carry chain input/output must be last input/output,
-#        swapped with what normally would have been the last
-#        output, here: CI <-> S, CO <-> O
+#   (NB: carry chain input/output must be last
+#        input/output and have been moved there
+#        overriding the alphabetical ordering)
 CARRY4 3 1 10 8
-223 -   -   -   482 -   -   -   -   222
-400 205 -   -   598 407 -   -   -   334
-523 558 226 -   584 556 537 -   -   239
-582 618 330 227 642 615 596 438 -   313
-340 -   -   -   536 379 -   -   -   271
-433 469 -   -   494 465 445 -   -   157
-512 548 292 -   592 540 520 356 -   228
-508 528 378 380 580 526 507 398 385 114
+482 -   -   -   -   223 -   -   -   222
+598 407 -   -   -   400 205 -   -   334
+584 556 537 -   -   523 558 226 -   239
+642 615 596 438 -   582 618 330 227 313
+536 379 -   -   -   340 -   -   -   271
+494 465 445 -   -   433 469 -   -   157
+592 540 520 356 -   512 548 292 -   228
+580 526 507 398 385 508 528 378 380 114