sim.blackboxes.serial: add missing Verilog blackbox.
authorJean-François Nguyen <jf@lambdaconcept.com>
Fri, 29 Oct 2021 18:36:52 +0000 (20:36 +0200)
committerJean-François Nguyen <jf@lambdaconcept.com>
Fri, 29 Oct 2021 18:36:52 +0000 (20:36 +0200)
lambdasoc/sim/blackboxes/serial/blackbox.v [new file with mode: 0644]

diff --git a/lambdasoc/sim/blackboxes/serial/blackbox.v b/lambdasoc/sim/blackboxes/serial/blackbox.v
new file mode 100644 (file)
index 0000000..b4df604
--- /dev/null
@@ -0,0 +1,26 @@
+(* cxxrtl_blackbox, cxxrtl_template = "DATA_BITS" *)
+module serial_rx(...);
+       parameter ID = "";
+       parameter DATA_BITS = 8;
+
+       (* cxxrtl_edge = "p" *) input clk;
+       input rst;
+       (* cxxrtl_sync, cxxrtl_width = "DATA_BITS" *) output [DATA_BITS - 1:0] data;
+       (* cxxrtl_sync *) output err_overflow;
+       (* cxxrtl_sync *) output err_frame;
+       (* cxxrtl_sync *) output err_parity;
+       (* cxxrtl_sync *) output rdy;
+       input ack;
+endmodule
+
+(* cxxrtl_blackbox, cxxrtl_template = "DATA_BITS" *)
+module serial_tx(...);
+       parameter ID = "";
+       parameter DATA_BITS = 8;
+
+       (* cxxrtl_edge = "p" *) input clk;
+       input rst;
+       (* cxxrtl_width = "DATA_BITS" *) input [DATA_BITS - 1:0] data;
+       (* cxxrtl_sync *) output rdy;
+       input ack;
+endmodule