docs: cover `nmigen.lib.cdc`.

diff --git a/docs/conf.py b/docs/conf.py
index 234fcb830ee23fa71f52452e0bd92499e8acd4c3..6b555c6c25cfe3a3531ad600408357047065fb02 100644 (file)
--- a/docs/conf.py
+++ b/docs/conf.py
@@ -30,6 +30,7 @@ todo_include_todos = True
 napoleon_google_docstring = False
 napoleon_numpy_docstring = True
 napoleon_use_ivar = True
+napoleon_custom_sections = ["Platform overrides"]
 
 html_theme = "sphinx_rtd_theme"
 html_static_path = ["_static"]

diff --git a/docs/stdlib.rst b/docs/stdlib.rst
index 333db16cad7abe2341bb42111128a552cc147d3d..5dafaddfa199f4f3ed452e1a75ce1938df8f890d 100644 (file)
--- a/docs/stdlib.rst
+++ b/docs/stdlib.rst
@@ -9,3 +9,4 @@ Standard library
    :maxdepth: 2
 
    stdlib/coding
+   stdlib/cdc

diff --git a/docs/stdlib/cdc.rst b/docs/stdlib/cdc.rst
new file mode 100644 (file)
index 0000000..596e69d
--- /dev/null
+++ b/docs/stdlib/cdc.rst
@@ -0,0 +1,13 @@
+Clock domain crossing
+#####################
+
+.. py:module:: nmigen.lib.cdc
+
+The ``nmigen.lib.cdc`` package provides modules for transferring data between clock domains.
+
+
+.. autoclass:: FFSynchronizer()
+.. autoclass:: AsyncFFSynchronizer()
+.. autoclass:: ResetSynchronizer()
+.. autoclass:: PulseSynchronizer()
+

diff --git a/nmigen/lib/cdc.py b/nmigen/lib/cdc.py
index a3f35f3d25c5f6e3c94cfba38cfb9e61243a93f9..4bc52523a34c8a75f4531c523c5bbbbb562ff1b8 100644 (file)
--- a/nmigen/lib/cdc.py
+++ b/nmigen/lib/cdc.py
@@ -195,8 +195,8 @@ class ResetSynchronizer(Elaboratable):
         Maximum delay from the input signal's clock to the first synchronization stage, in seconds.
         If specified and the platform does not support it, elaboration will fail.
 
-    Platform override
-    -----------------
+    Platform overrides
+    ------------------
     Define the ``get_reset_sync`` platform method to override the implementation of
     :class:`ResetSynchronizer`, e.g. to instantiate library cells directly.
     """
@@ -219,9 +219,9 @@ class PulseSynchronizer(Elaboratable):
     """A one-clock pulse on the input produces a one-clock pulse on the output.
 
     If the output clock is faster than the input clock, then the input may be safely asserted at
-    100% duty cycle. Otherwise, if the clock ratio is `n`:1, the input may be asserted at most once
-    in every `n` input clocks, else pulses may be dropped. Other than this there is no constraint
-    on the ratio of input and output clock frequency.
+    100% duty cycle. Otherwise, if the clock ratio is ``n``:1, the input may be asserted at most
+    once in every ``n`` input clocks, else pulses may be dropped. Other than this there is
+    no constraint on the ratio of input and output clock frequency.
 
     Parameters
     ----------