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diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index 39892e774adb74763c7daf88130f82a8656bc533..f5a2175ce22c16386e58b6a4eea1bbc86d84299f 100644 (file)
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -91,7 +91,7 @@ Table 9: Primary Opcode Map (opcode bits 0:5)
     111 |  lq    | EXT57 | EXT58 | EXT59 | EXT60 | EXT61  | EXT62 | EXT63 | 111
         |  000   |   001 |   010 |  011  |   100 |   101  | 110   |  111
 
-## Suitable for svp64
+## Suitable for svp64-only
 
 This is the same table containing v3.0B Primary Opcodes except those that
 make no sense in a Vectorisation Context have been removed.  These removed
@@ -113,6 +113,10 @@ retain their v3.0B / v3.1B OpenPOWER Standard compliant meaning.
     111 |        |       | EXT58 | EXT59 |       | EXT61  |       | EXT63 | 111
         |  000   |   001 |   010 |  011  |   100 |   101  | 110   |  111
 
+It is important to note that having a different v3.0B Scalar opcode
+that is different from an SVP64 one is highly undesirable: the complexity
+in the decoder is greatly increased.
+
 # Single Predication
 
 This is a standard mode normally found in Vector ISAs.  every element in rvery source Vector and in the destination uses the same bit of one single predicate mask.