generic_platform: do not create clock domains during Verilog conversion

diff --git a/mibuild/generic_platform.py b/mibuild/generic_platform.py
index d3fe50b22439dc229d0be0cd01d2cf299749b885..fcbe7ba3f8a86c7c491a8fd7f60f9f936deca19e 100644 (file)
--- a/mibuild/generic_platform.py
+++ b/mibuild/generic_platform.py
@@ -214,7 +214,8 @@ class GenericPlatform:
                        else:
                                frag = fragment
                        # generate Verilog
-                       src, vns = verilog.convert(frag, self.constraint_manager.get_io_signals(), return_ns=True, **kwargs)
+                       src, vns = verilog.convert(frag, self.constraint_manager.get_io_signals(),
+                               return_ns=True, create_clock_domains=False, **kwargs)
                        # resolve signal names in constraints
                        sc = self.constraint_manager.get_sig_constraints()
                        named_sc = [(vns.get_name(sig), pins, others, resource) for sig, pins, others, resource in sc]