The interpretation of the fields is different depending whether the
instruction is a SEND/MATH or not.
This fixes the disassembly output for non-SEND/MATH instructions that
have both in-order and out-of-order dependencies. Their dependencies
were wrongly represented as `@A $B` when the correct would be `@A
$B.dst`.
Fixes: 6154cdf924f ("intel/eu/gen12: Add auxiliary type to represent SWSB information during codegen.")
Fixes: 83612c01271 ("intel/disasm/gen12: Disassemble software scoreboard information.")
Acked-by: Francisco Jerez <currojerez@riseup.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3660>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3660>
static int
swsb(FILE *file, const struct gen_device_info *devinfo, const brw_inst *inst)
{
- const struct tgl_swsb swsb = tgl_swsb_decode(brw_inst_swsb(devinfo, inst));
+ const struct tgl_swsb swsb = tgl_swsb_decode(brw_inst_opcode(devinfo, inst),
+ brw_inst_swsb(devinfo, inst));
if (swsb.regdist)
format(file, " @%d", swsb.regdist);
if (swsb.mode)
* tgl_swsb.
*/
static inline struct tgl_swsb
-tgl_swsb_decode(uint8_t x)
+tgl_swsb_decode(enum opcode opcode, uint8_t x)
{
if (x & 0x80) {
const struct tgl_swsb swsb = { (x & 0x70u) >> 4, x & 0xfu,
- TGL_SBID_DST | TGL_SBID_SET };
+ (opcode == BRW_OPCODE_SEND ||
+ opcode == BRW_OPCODE_SENDC ||
+ opcode == BRW_OPCODE_MATH) ?
+ TGL_SBID_SET : TGL_SBID_DST };
return swsb;
} else if ((x & 0x70) == 0x20) {
return tgl_swsb_sbid(TGL_SBID_DST, x & 0xfu);