add twin src and dest flen instruction testing

WRITE_FREG and READ_FREG need different flen inputs.  start differentiating

diff --git a/id_regs.py b/id_regs.py
index 86d4db9e56c5165da6a51158fe6adbab61dc481c..61fde4a05c958937eb73df7c96351afb0a3a01c3 100644 (file)
--- a/id_regs.py
+++ b/id_regs.py
@@ -56,7 +56,8 @@ allints = intpatterns + cintpatterns[2:] # skip the WRITE_RVC_xx ones
 
 skip = '#define USING_NOREGS\n' \
        '#define REGS_PATTERN 0x0\n' \
-       '#define INSN_FLEN 0\n'
+       '#define INSN_SRC_FLEN 0\n' \
+       '#define INSN_DEST_FLEN 0\n'
 
 # this matches the order of the 5 predication arguments to
 drlookup = { 'rd': 0, 'frd': 0, 'rs1': 1, 'rs2': 2, 'rs3': 3,
@@ -80,17 +81,34 @@ def find_registers(fname, insn, twin_predication, immed_offset, is_branch):
     with open(fname) as f:
         f = f.read()
         dest_reg = None
-        flen = 0
-        if "f128(" in f:
-            flen = 128
+        src_flen = 0
+        dest_flen = 0
+        split = insn.split('_')
+        if len(split) == 3 and split[0].startswith('f'):
+            if split[2].startswith('w'):
+                src_flen = 32
+                dest_flen = 32
+            elif split[2].startswith('d'):
+                src_flen = 64
+                dest_flen = 64
+            elif split[2].startswith('q'):
+                src_flen = 128
+                dest_flen = 128
+            if split[1].startswith('w'):
+                src_flen = 32
+            elif split[1].startswith('d'):
+                src_flen = 64
+            elif split[1].startswith('q'):
+                src_flen = 128
+        elif "f128(" in f:
+            src_flen = 128
+            dest_flen = 128
         elif "f64(" in f:
-            flen = 64
+            src_flen = 64
+            dest_flen = 64
         elif "f32(" in f:
-            flen = 32
-        elif insn == 'fmv_x_w':
-            flen = 32
-        elif insn == 'fmv_x_d':
-            flen = 64
+            src_flen = 32
+            dest_flen = 32
         for pattern in patterns:
             x = f.find(pattern)
             if x == -1:
@@ -139,7 +157,8 @@ def find_registers(fname, insn, twin_predication, immed_offset, is_branch):
     if not res:
         return skip
     res.append('#define REGS_PATTERN 0x%x' % isintfloat)
-    res.append('#define INSN_FLEN %d' % flen)
+    res.append('#define INSN_SRC_FLEN %d' % src_flen)
+    res.append('#define INSN_DEST_FLEN %d' % dest_flen)
 
     predargs = ['dest_pred'] * 5
     if immed_offset: # C.LWSP

diff --git a/riscv/insn_template_sv.cc b/riscv/insn_template_sv.cc
index 6309c412d0eefc86494506667d1a48ec0a777451..61b4abd015369129ff0f898b56bb716d3e872caf 100644 (file)
--- a/riscv/insn_template_sv.cc
+++ b/riscv/insn_template_sv.cc
@@ -63,7 +63,8 @@ reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc)
   reg_t target_pred = ~0x0;
   bool zeroingtarg = false;
 #endif
-  sv_insn_t insn(p, sv_enabled, bits, floatintmap, xlen, INSN_FLEN,
+  sv_insn_t insn(p, sv_enabled, bits, floatintmap, xlen,
+                 INSN_SRC_FLEN, INSN_DEST_FLEN,
                  PRED_ARGS, OFFS_ARGS,
 #ifdef INSN_TYPE_SIGNED
                  true

diff --git a/riscv/sv.cc b/riscv/sv.cc
index 18a4e7c52f028140b56f2a4cd5c9c628dd2fb01d..f5af8666e92c1cc8ae0833847bab5b3cafcb03b9 100644 (file)
--- a/riscv/sv.cc
+++ b/riscv/sv.cc
@@ -21,13 +21,15 @@ uint8_t maxelwidth(uint8_t wid1, uint8_t wid2)
 }
 
 sv_insn_t::sv_insn_t(processor_t *pr, bool _sv_enabled,
-            insn_bits_t bits, unsigned int f, int _xlen, int _flen,
+            insn_bits_t bits, unsigned int f,
+            int _xlen, int _src_flen, int _dest_flen,
             uint64_t &p_rd, uint64_t &p_rs1, uint64_t &p_rs2, uint64_t &p_rs3,
             uint64_t &p_sp, uint64_t *p_im,
             int *o_rd, int *o_rs1, int *o_rs2, int *o_rs3, int *o_sp,
             int *o_imm,
             bool _sign) :
-            insn_t(bits), p(pr), src_bitwidth(0), xlen(_xlen), flen(_flen),
+            insn_t(bits), p(pr), src_bitwidth(0),
+            xlen(_xlen), src_flen(_src_flen), dest_flen(_dest_flen),
             sv_enabled(_sv_enabled), signextended(_sign),
             vloop_continue(false),
             at_least_one_reg_vectorised(false), fimap(f),

diff --git a/riscv/sv_decode.h b/riscv/sv_decode.h
index d449bc7c42317a4e1263bc94aa02a818cfb2abdc..f9551e8d23f2cc463a5651ba53ae333d310dc4ea 100644 (file)
--- a/riscv/sv_decode.h
+++ b/riscv/sv_decode.h
@@ -38,7 +38,7 @@ class sv_insn_t: public insn_t
 {
 public:
   sv_insn_t(processor_t *pr, bool _sv_enabled, insn_bits_t bits, unsigned int f,
-            int xlen, int flen,
+            int xlen, int src_flen, int dest_flen,
             uint64_t &p_rd, uint64_t &p_rs1, uint64_t &p_rs2, uint64_t &p_rs3,
             uint64_t &p_sp, uint64_t *p_im,
             int *o_rd, int *o_rs1, int *o_rs2, int *o_rs3, int *o_sp,
@@ -102,7 +102,8 @@ public:
   processor_t *p;
   uint8_t src_bitwidth;
   int xlen;
-  int flen;
+  int src_flen;
+  int dest_flen;
   bool sv_enabled;
   bool signextended;
 

diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc
index 6d4de6714e8afbe3ff983519dd20c1d8e2f99184..c4d5b9e00d6c517b47084e0f5d25ab1a442063c4 100644 (file)
--- a/riscv/sv_insn_redirect.cc
+++ b/riscv/sv_insn_redirect.cc
@@ -120,11 +120,17 @@ union freg_shift {
 
 void (sv_proc_t::DO_WRITE_FREG)(reg_spec_t const& spec, sv_freg_t const& value)
 {
-    //int flen = sizeof(freg_t) * 8; // FLEN (not specified in spike)
-    int flen = _insn->flen;
+    int regflen = sizeof(freg_t) * 8; // FLEN (not specified in spike)
+    int flen = _insn->dest_flen;
     reg_t reg = spec.reg;
     uint8_t dest_elwidth = _insn->reg_elwidth(reg, false);
-    int bitwidth = get_bitwidth(dest_elwidth, flen);
+    int bitwidth = 0;
+    //if (_insn->sv_check_reg(reg, false)) {
+        bitwidth = get_bitwidth(dest_elwidth, flen);
+    //} else {
+    //    bitwidth = regflen;
+    //    flen = regflen;
+    //}
     fprintf(stderr, "DO_WRITE_FRD rd %ld ew %d data %lx %lx\n",
             reg, dest_elwidth, ((freg_t)value).v[0], ((freg_t)value).v[1]);
     unsigned int shift = 0;
@@ -142,7 +148,7 @@ void (sv_proc_t::DO_WRITE_FREG)(reg_spec_t const& spec, sv_freg_t const& value)
         throw trap_illegal_instruction(0);
     }
     freg_shift fd;
-    if (xlen != bitwidth)
+    if (flen != bitwidth)
     {
         char report[2] = {};
         freg_shift fs;
@@ -224,7 +230,7 @@ void (sv_proc_t::WRITE_REG)(reg_spec_t const& spec, sv_reg_t const& value)
 freg_t (sv_proc_t::READ_FREG)(reg_spec_t const& spec)
 {
     int regflen = sizeof(freg_t) * 8; // FLEN (not specified in spike)
-    int flen = _insn->flen;
+    int flen = _insn->src_flen;
     reg_t reg = spec.reg;
     uint8_t elwidth = _insn->reg_elwidth(reg, false);
     int bitwidth = get_bitwidth(elwidth, flen);