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diff --git a/openpower/sv/executive_summary.mdwn b/openpower/sv/executive_summary.mdwn
index 41622bd2cda50f935f259a70bf7bf3ece5f58a1c..fb8d8714ae9c19c629b10b2dffa11cf92c0be22c 100644 (file)
--- a/openpower/sv/executive_summary.mdwn
+++ b/openpower/sv/executive_summary.mdwn
@@ -1,13 +1,12 @@
 
-
 Simple-V is a Scalable Vector ISA Extension specifically for the Power ISA.
 It is extremely important to think of Simple-V as a 2-Dimensional ISA:
-instructions vertical and registers horizontal, otherwise it will be
+instructions vertical and registers horizontal otherwise it will be
 difficult to understand.
 
 Simple-V is **not RISC-V and is not RISC-V Vectors**. NEC SX Aurora,
 RVV and Simple-V are all based on Cray-style Vectors hence the similarity,
-the provision of a `setvl` instruction and why they are called
+the provision of a `setvl` instruction and why they are each called
 "Scalable" Vectors because it is the `setvl` instruction that
 presents the programmer with explicit control over Vector length.
 
@@ -18,4 +17,12 @@ hot-loops.
 
 Links to Simulator and Unit tests:
 
-* Simple-V Simulator 
+* Unit tests and simulator for Power ISA v3.0 and SVP64
+  <https://git.libre-soc.org/?p=openpower-isa.git;a=tree;f=src/openpower/decoder/isa;hb=HEAD>
+* several thousand more ISA unit tests
+  <https://git.libre-soc.org/?p=openpower-isa.git;a=tree;f=src/openpower/test;hb=HEAD>
+* demo, showing 4.5x reduction in program size for MP3 decode, greatly
+  simplifies assembler development
+  <https://git.libre-soc.org/?p=openpower-isa.git;a=tree;f=media/audio/mp3;hb=HEAD>
+* binutils support for SVP64 
+  <https://git.libre-soc.org/?p=binutils-gdb.git;a=shortlog;h=refs/heads/svp64-ng>