Add ice40 box files

diff --git a/techlibs/ice40/Makefile.inc b/techlibs/ice40/Makefile.inc
index 723b59d6f661b8e7e16477031b68373a43e35524..cd992bb248388e17b894892d514f20f1b973c475 100644 (file)
--- a/techlibs/ice40/Makefile.inc
+++ b/techlibs/ice40/Makefile.inc
@@ -28,6 +28,9 @@ $(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_sim.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/latches_map.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams.txt))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams_map.v))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/cells.box))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_box.v))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/lut.lut))
 
 $(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init1.vh))
 $(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init2.vh))

diff --git a/techlibs/ice40/cells.box b/techlibs/ice40/cells.box
new file mode 100644 (file)
index 0000000..e4cfb71
--- /dev/null
+++ b/techlibs/ice40/cells.box
@@ -0,0 +1,6 @@
+# NB: Inputs/Outputs must be ordered alphabetically
+
+# Inputs: CI I0 I1
+# Outputs: CO
+SB_CARRY 1 1 3 1
+126 259 231

diff --git a/techlibs/ice40/cells_box.v b/techlibs/ice40/cells_box.v
new file mode 100644 (file)
index 0000000..cca88f9
--- /dev/null
+++ b/techlibs/ice40/cells_box.v
@@ -0,0 +1,5 @@
+(* abc_box_id = 1 *)
+module SB_CARRY (output CO, input CI, I0, I1);
+       assign CO = (I0 && I1) || ((I0 || I1) && CI);
+endmodule
+

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 62a28364ba0bc33943260c44adabeb4e5d13fe70..322c1e5c7da5c158b533bf1a4f2aa1f743d5d1c4 100644 (file)
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -881,6 +881,7 @@ module SB_WARMBOOT (
 );
 endmodule
 
+(* nomem2reg *)
 module SB_SPRAM256KA (
        input [13:0] ADDRESS,
        input [15:0] DATAIN,

diff --git a/techlibs/ice40/lut.lut b/techlibs/ice40/lut.lut
new file mode 100644 (file)
index 0000000..48da89f
--- /dev/null
+++ b/techlibs/ice40/lut.lut
@@ -0,0 +1,4 @@
+1      1       316
+2      1       316 379
+3      1       316 379 400
+4      1       316     379     400     449

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 6c77e5482068fd0d64c9903aa0b17ab46c4fcfce..3faa10b4f90560b49e7724414a4c29ff0ce95854 100644 (file)
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -316,7 +316,14 @@ struct SynthIce40Pass : public ScriptPass
                                run("techmap -map +/gate2lut.v -D LUT_WIDTH=4", "(only if -noabc)");
                        }
                        if (!noabc) {
-                               run(abc + " -dress -lut 4", "(skip if -noabc)");
+                               if (abc == "abc9") {
+                                       run("read_verilog +/ice40/cells_box.v");
+                                       run("techmap -map +/techmap.v A:abc_box_id");
+                                       run(abc + " -dress -lut +/ice40/lut.lut -box +/ice40/cells.box", "(skip if -noabc)");
+                                       run("blackbox A:abc_box_id");
+                               }
+                               else
+                                       run(abc + " -lut 4", "(skip if -noabc)");
                        }
                        run("clean");
                        if (relut || help_mode) {