(no commit message)

diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
index f7415503a59820777831c7f8374586cae88cf722..18c8d0319980446a586ef25ed1ba0894d55b8394 100644 (file)
--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
@@ -65,9 +65,6 @@ Other modes are still applicable and include:
 for analysing a Vector of Condition Register Fields
 and reducing it to one
 single Condition Register Field.
-* **Pack/Unpack Mode**.
-  Like VSX `vpack` and `vunpack` the source and destination
-  elements are reordered.
 
 Predicate-result does not make any sense because
 when Rc=1 a co-result is created (a CR Field). Testing the co-result
@@ -84,6 +81,7 @@ SVP64 RM `MODE` (includes `ELWIDTH_SRC` bits) for CR-based operations:
 |sz |SNZ| 0 RG  |   0 | dz  /   | simple mode                      |
 |sz |SNZ| 0 RG  |   1 | 0   /   | scalar reduce mode (mapreduce), SUBVL=1 |
 |zz |SNZ| 0 RG  |   1 | SVM 0   | subvector reduce mode, SUBVL>1   |
+|zz |SNZ| 0 RG  |   1 | /   1   | reserved   |
 |zz |SNZ| 1 VLI | inv |  CR-bit | Ffirst 3-bit mode      |
 |sz |SNZ| 1 VLI | inv |  dz /   | Ffirst 5-bit mode       |