litex.build: update from migen.genlib.io litex.build.io.

diff --git a/litex/boards/targets/minispartan6.py b/litex/boards/targets/minispartan6.py
index 2903a5074a81155addb2e6b229ec17f400edf139..408ed442c0063f1c5dc6595e6c47f6d01c680491 100755 (executable)
--- a/litex/boards/targets/minispartan6.py
+++ b/litex/boards/targets/minispartan6.py
@@ -9,9 +9,9 @@ import argparse
 from fractions import Fraction
 
 from migen import *
-from migen.genlib.io import DDROutput
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
+from litex.build.io import DDROutput
 from litex.boards.platforms import minispartan6
 
 from litex.soc.cores.clock import *

diff --git a/litex/build/altera/common.py b/litex/build/altera/common.py
index 45770984b846372592146551190f12d5776e1354..252f5fbd4277c04a273c7ad52a6c3d207f003561 100644 (file)
--- a/litex/build/altera/common.py
+++ b/litex/build/altera/common.py
@@ -2,12 +2,12 @@
 # This file is Copyright (c) 2019 vytautasb <v.buitvydas@limemicro.com>
 # License: BSD
 
+from migen import *
 from migen.fhdl.module import Module
 from migen.fhdl.specials import Instance
-from migen.genlib.io import DifferentialInput, DifferentialOutput
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from migen.fhdl.structure import *
+from litex.build.io import *
 
 # DifferentialInput --------------------------------------------------------------------------------
 

diff --git a/litex/build/lattice/common.py b/litex/build/lattice/common.py
index 6b340c8dbb45c01e5e26d3b6dc8f53d20d3e520e..52286dda0052d717f3f5beedbdbeba610049c3d2 100644 (file)
--- a/litex/build/lattice/common.py
+++ b/litex/build/lattice/common.py
@@ -6,10 +6,9 @@
 from migen.fhdl.module import Module
 from migen.fhdl.specials import Instance, Tristate
 from migen.fhdl.bitcontainer import value_bits_sign
-from migen.genlib.io import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex.gen.io import *
+from litex.build.io import *
 
 # ECP5 AsyncResetSynchronizer ----------------------------------------------------------------------
 

diff --git a/litex/build/xilinx/common.py b/litex/build/xilinx/common.py
index bc6c96d50a3ce3e13b34d99015a63c5d29606f53..0017f623e9af3a45517898679e5f5b7b5cdefa68 100644 (file)
--- a/litex/build/xilinx/common.py
+++ b/litex/build/xilinx/common.py
@@ -13,8 +13,8 @@ from migen.fhdl.specials import Instance
 from migen.fhdl.module import Module
 from migen.genlib.cdc import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
-from migen.genlib.io import *
 
+from litex.build.io import *
 from litex.build import tools
 
 # Colorama -----------------------------------------------------------------------------------------

diff --git a/litex/soc/cores/clock.py b/litex/soc/cores/clock.py
index 2ff7668c930e3cac85a32d344c23733a190471ed..97f83c7ba6631d2967afcc5febb2ac4717585a7f 100644 (file)
--- a/litex/soc/cores/clock.py
+++ b/litex/soc/cores/clock.py
@@ -8,9 +8,10 @@ import math
 import logging
 
 from migen import *
-from migen.genlib.io import DifferentialInput
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
+from litex.build.io import DifferentialInput
+
 from litex.soc.integration.soc import colorer
 from litex.soc.interconnect.csr import *
 

diff --git a/litex/soc/cores/hyperbus.py b/litex/soc/cores/hyperbus.py
index c1dc0b8cd0bbcc703c8e47a5dac09af3ec068959..cfc813104b91579e20c7447e645d23b450a4de5a 100644 (file)
--- a/litex/soc/cores/hyperbus.py
+++ b/litex/soc/cores/hyperbus.py
@@ -4,7 +4,8 @@
 
 from migen import *
 from migen.genlib.misc import timeline
-from migen.genlib.io import DifferentialOutput
+
+from litex.build.io import DifferentialOutput
 
 from litex.soc.interconnect import wishbone