O3: Send instruction back to fetch on squash to seed predecoder correctly.

diff --git a/src/arch/alpha/predecoder.hh b/src/arch/alpha/predecoder.hh
index a8788051f3ec634bf7608f7b18cf037c54b7dc8a..2f8c4c2ef1dab8cfe945d9e14942890c102a6f1b 100644 (file)
--- a/src/arch/alpha/predecoder.hh
+++ b/src/arch/alpha/predecoder.hh
@@ -76,6 +76,12 @@ class Predecoder
         emiIsReady = false;
     }
 
+    void
+    reset(const ExtMachInst &old_emi)
+    {
+        reset();
+    }
+
     // Use this to give data to the predecoder. This should be used
     // when there is control flow.
     void

diff --git a/src/arch/arm/predecoder.hh b/src/arch/arm/predecoder.hh
index a99e38ce70adc83ddce11145de1d5e0599f30f5c..511bc29bc9427cbece8aa02f0df9712eeb4b81e3 100644 (file)
--- a/src/arch/arm/predecoder.hh
+++ b/src/arch/arm/predecoder.hh
@@ -83,6 +83,12 @@ namespace ArmISA
             predAddrValid = false;
         }
 
+        void reset(const ExtMachInst &old_emi)
+        {
+            reset();
+            itstate = old_emi.newItstate;
+        }
+
         Predecoder(ThreadContext * _tc) :
             tc(_tc), data(0)
         {

diff --git a/src/arch/mips/predecoder.hh b/src/arch/mips/predecoder.hh
index 4220b768c6fd0ebefce55531492b334d8caaf147..110493cc54ea2ba258823a0e3d8ae99ed291f781 100644 (file)
--- a/src/arch/mips/predecoder.hh
+++ b/src/arch/mips/predecoder.hh
@@ -75,6 +75,12 @@ class Predecoder
         emiIsReady = false;
     }
 
+    void
+    reset(const ExtMachInst &old_emi)
+    {
+        reset();
+    }
+
     //Use this to give data to the predecoder. This should be used
     //when there is control flow.
     void

diff --git a/src/arch/power/predecoder.hh b/src/arch/power/predecoder.hh
index 8b10890957a04a1ce5008ab922acd9c02ccb4909..c10bc51bf7a61032305ee0850639559ed4fd8351 100644 (file)
--- a/src/arch/power/predecoder.hh
+++ b/src/arch/power/predecoder.hh
@@ -82,6 +82,12 @@ class Predecoder
         emiIsReady = false;
     }
 
+    void
+    reset(const ExtMachInst &old_emi)
+    {
+        reset();
+    }
+
     // Use this to give data to the predecoder. This should be used
     // when there is control flow.
     void

diff --git a/src/arch/sparc/predecoder.hh b/src/arch/sparc/predecoder.hh
index 670c547d095aca41dd40e3555f18122cf80e56cf..082adeb7296d643c75b47d9978ec3724bf90c072 100644 (file)
--- a/src/arch/sparc/predecoder.hh
+++ b/src/arch/sparc/predecoder.hh
@@ -68,12 +68,19 @@ class Predecoder
     }
 
     void process() {}
+
     void
     reset()
     {
         emiIsReady = false;
     }
 
+    void
+    reset(const ExtMachInst &old_emi)
+    {
+        reset();
+    }
+
     // Use this to give data to the predecoder. This should be used
     // when there is control flow.
     void

diff --git a/src/arch/x86/predecoder.hh b/src/arch/x86/predecoder.hh
index 5c67e28e19acf28498f88635649abfbf8052c011..790453b98ef1279c0c17acc4aabe5da75bb96023 100644 (file)
--- a/src/arch/x86/predecoder.hh
+++ b/src/arch/x86/predecoder.hh
@@ -174,6 +174,12 @@ namespace X86ISA
             state = ResetState;
         }
 
+        void
+        reset(const ExtMachInst &old_emi)
+        {
+            reset();
+        }
+
         ThreadContext * getTC()
         {
             return tc;

diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 2d3bc3f724c2b9a7364812d6be6204b97059f595..4088f23995b73de23dc110121345b29d979b93da 100644 (file)
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -808,8 +808,9 @@ FullO3CPU<Impl>::removeThread(ThreadID tid)
     }
 
     // Squash Throughout Pipeline
-    InstSeqNum squash_seq_num = commit.rob->readHeadInst(tid)->seqNum;
-    fetch.squash(0, squash_seq_num, tid);
+    DynInstPtr inst = commit.rob->readHeadInst(tid);
+    InstSeqNum squash_seq_num = inst->seqNum;
+    fetch.squash(0, squash_seq_num, inst, tid);
     decode.squash(tid);
     rename.squash(squash_seq_num, tid);
     iew.squash(tid);

diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index c5165810449a40057fff476381347c3d507c6fa9..4a4ac09021f26406fec8a6be36a265ce0a71c3cd 100644 (file)
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -312,8 +312,8 @@ class DefaultFetch
      * remove any instructions that are not in the ROB. The source of this
      * squash should be the commit stage.
      */
-    void squash(const TheISA::PCState &newPC,
-                const InstSeqNum &seq_num, ThreadID tid);
+    void squash(const TheISA::PCState &newPC, const InstSeqNum &seq_num,
+                DynInstPtr &squashInst, ThreadID tid);
 
     /** Ticks the fetch stage, processing all inputs signals and fetching
      * as many instructions as possible.

diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 5f9be039fc90be422dd53bb39dcabdc5877dcad8..6c1ac456d0ab85c57048b1569134e221f621809a 100644 (file)
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -815,11 +815,14 @@ DefaultFetch<Impl>::updateFetchStatus()
 template <class Impl>
 void
 DefaultFetch<Impl>::squash(const TheISA::PCState &newPC,
-                           const InstSeqNum &seq_num, ThreadID tid)
+                           const InstSeqNum &seq_num, DynInstPtr &squashInst,
+                           ThreadID tid)
 {
     DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n", tid);
 
     doSquash(newPC, tid);
+    if (squashInst)
+        predecoder.reset(squashInst->staticInst->machInst);
 
     // Tell the CPU to remove any instructions that are not in the ROB.
     cpu->removeInstsNotInROB(tid);

diff --git a/src/kern/linux/events.cc b/src/kern/linux/events.cc
index f619dd11b5740b97b6ce7ba2520af01e3dcf0b88..60aa857acac8cafb832910ebd2338614ea1a0378 100644 (file)
--- a/src/kern/linux/events.cc
+++ b/src/kern/linux/events.cc
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2011 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2004-2006 The Regents of The University of Michigan
  * All rights reserved.
  *