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+Date: Tue, 26 May 2020 02:03:56 +0000
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+X-Bugzilla-Product: Libre-SOC's first SoC
+X-Bugzilla-Component: Source Code
+X-Bugzilla-Version: unspecified
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+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: lkcl@lkcl.net
+X-Bugzilla-Status: CONFIRMED
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+Message-ID: <bug-351-13-a7L5PXZtf1@https.bugs.libre-soc.org/>
+In-Reply-To: <bug-351-13@https.bugs.libre-soc.org/>
+References: <bug-351-13@https.bugs.libre-soc.org/>
+X-Bugzilla-URL: https://bugs.libre-soc.org/
+Auto-Submitted: auto-generated
+MIME-Version: 1.0
+Subject: [libre-riscv-dev] [Bug 351] create a "block" (mass) regfile port
+ (read and write) onto an array-based regfile
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