# Record Size
record_size = 1024
+csr = Uart2Spi(1,115200)
+
# Csr Addr
MIGIO0_ADDR = 0x0000
-TRIGGER_ADDR = 0x0200
-RECORDER_ADDR = 0x0400
# MigScope Configuration
# migIo
-migIo0 = migIo.MigIo(MIGIO0_ADDR, 8, "IO")
-
-# Trigger
-term0 = trigger.Term(trig_width)
-trigger0 = trigger.Trigger(TRIGGER_ADDR, trig_width, dat_width, [term0])
-
-# Recorder
-recorder0 = recorder.Recorder(RECORDER_ADDR, dat_width, record_size)
+migIo0 = migIo.MigIo(MIGIO0_ADDR, 8, "IO", csr)
#==============================================================================
# T E S T M I G I O
#==============================================================================
-csr = Uart2Spi(1,115200)
-
print("1) Write Led Reg")
for i in range(10):
- csr.write(MIGIO0_ADDR + 0,0xA5)
+ migIo0.write(0xA5)
time.sleep(0.1)
- csr.write(MIGIO0_ADDR + 0,0x5A)
+ migIo0.write(0x5A)
time.sleep(0.1)
print("2) Read Switch Reg")
-print(csr.read(MIGIO0_ADDR + 1))
+print(migIo0.read())
\ No newline at end of file
# Trigger
term0 = trigger.Term(trig_width)
- trigger0 = trigger.Trigger(TRIGGER_ADDR, trig_width, dat_width, [term0])
+ term1 = trigger.Term(trig_width)
+ term2 = trigger.Term(trig_width)
+ term3 = trigger.Term(trig_width)
+
+ trigger0 = trigger.Trigger(TRIGGER_ADDR, trig_width, dat_width, [term0, term1, term2, term3])
# Recorder
recorder0 = recorder.Recorder(RECORDER_ADDR, dat_width, record_size)
# Spi2Csr
- spi2csr0 = spi2Csr.Spi2Csr(16,8)
+ spi2csr0 = spi2Csr.Spi2Csr(14,8)
# Csr Interconnect
csrcon0 = csr.Interconnect(spi2csr0.csr,
# Signal Generator
sig_gen = Signal(BV(trig_width))
- sync += [
- sig_gen.eq(sig_gen+1)
- ]
+ #sync += [
+ # sig_gen.eq(sig_gen+1)
+ #]
# Led
led0 = Signal(BV(8))
- comb += [led0.eq(migIo0.o)]
+ comb += [led0.eq(migIo0.o[:8])]
#Switch
sw0 = Signal(BV(8))
comb += [migIo0.i.eq(sw0)]
+ sync += [
+ sig_gen.eq(migIo0.o)
+ ]
# Dat / Trig Bus
comb += [
trigger0.in_trig.eq(sig_gen),
trigger0.in_dat.eq(sig_gen)
]
+ #comb += [led0[7].eq(trigger0.sum.i)]
+ #comb += [led0[6].eq(trigger0.sum.o)]
+
+ #comb += [led0[3].eq(term3.o)]
+ #comb += [led0[2].eq(term2.o)]
+ #comb += [led0[1].eq(term1.o)]
+ #comb += [led0[0].eq(term0.o)]
# Trigger --> Recorder
comb += [
class MigIo:
- def __init__(self,address, width, mode = "IO"):
+ def __init__(self,address, width, mode = "IO", interface=None):
self.address = address
self.width = width
self.mode = mode
+ self.interface = interface
+ self.words = int(2**bits_for(width-1)/8)
if "I" in self.mode:
self.i = Signal(BV(self.width))
self.ireg = description.RegisterField("i", self.width, READ_ONLY, WRITE_ONLY)
self.oreg = description.RegisterField("o", self.width)
self.oreg.field.r.name_override = "ouptuts"
self.bank = csrgen.Bank([self.oreg, self.ireg], address=self.address)
-
+
+ def write(self, data):
+ self.interface.write_n(self.address, data, self.width)
+
+ def read(self):
+ r = 0
+ r = self.interface.read_n(self.address + self.words, self.width)
+ return r
+
def get_fragment(self):
comb = []
if "I" in self.mode:
return Fragment(comb=comb, sync=sync)
class Recorder:
- def __init__(self,address, width, depth):
+ def __init__(self,address, width, depth, interface = None):
self.address = address
self.width = width
self.depth = depth
self.depth_width = bits_for(self.depth)
+ self.interface = interface
self.storage = Storage(self.width, self.depth)
self.sequencer = Sequencer(self.depth)
# Trigger Interface
self.trig_hit = Signal()
self.trig_dat = Signal(BV(self.width))
+
+ def reset(self):
+ self.interface.write(self.address + 0x00, 1)
+ self.interface.write(self.address + 0x00, 0)
+
+ def arm(self):
+ self.interface.write(self.address + 0x01, 1)
+
+ def is_done(self):
+ return self.interface.read(self.address + 0x02) == 1
+ def size(self, dat):
+ self.interface.write_n(self.address + 0x03, dat, 16)
+
+ def offset(self, dat):
+ self.interface.write_n(self.address + 0x05, dat, 16)
+
def get_fragment(self):
comb = []
sync = []
def __init__(self, width, pipe=False):
self.width = width
self.pipe = pipe
+ self.interface = None
self.reg_name = "term_reg"
self.reg_base = 0
self.reg_size = 1*width
+ self.words = int(2**bits_for(width-1)/8)
self.i = Signal(BV(self.width))
self.t = Signal(BV(self.width))
self.o = Signal()
+ def write(self, dat):
+ self.interface.write_n(self.reg_base, dat ,self.width)
+
def get_fragment(self):
frag = [
self.o.eq(self.i==self.t)
def __init__(self, width, pipe=False):
self.width = width
self.pipe = pipe
+ self.interface = None
self.reg_name = "range_reg"
self.reg_base = 0
self.reg_size = 2*width
+ self.words = int(2**bits_for(width-1)/8)
self.i = Signal(BV(self.width))
self.low = Signal(BV(self.width))
self.high = Signal(BV(self.width))
self.o = Signal()
+
+ def write_low(self, dat):
+ self.interface.write_n(self.reg_base, dat ,self.width)
+
+ def write_high(self, dat):
+ self.interface.write_n(self.reg_base + self.words, dat ,self.width)
def get_fragment(self):
frag = [
self.width = width
self.pipe = pipe
self.mode = mode
+ self.interface = None
self.reg_name = "edge_reg"
self.reg_base = 0
self.i = Signal(BV(self.width))
self.i_d = Signal(BV(self.width))
- if "R" in mode:
+ if "R" in self.mode:
self.r_mask = Signal(BV(self.width))
self.ro = Signal()
- if "F" in mode:
+ if "F" in self.mode:
self.f_mask = Signal(BV(self.width))
self.fo = Signal()
- if "B" in mode:
+ if "B" in self.mode:
self.b_mask = Signal(BV(self.width))
self.bo = Signal()
self.o = Signal()
+
+ def write_r(self, dat):
+ self.interface.write_n(self.reg_base, dat ,self.width)
+
+ def write_f(self, dat):
+ offset = 0
+ if "R" in self.mode:
+ offset += self.words
+ self.interface.write_n(self.reg_base + offset, dat ,self.width)
+
+ def write_b(self, dat):
+ if "R" in self.mode:
+ offset += self.words
+ if "F" in self.mode:
+ offset += self.words
+ self.interface.write_n(self.reg_base + offset, dat ,self.width)
def get_fragment(self):
comb = []
class Timer:
def __init__(self, width):
self.width = width
+ self.interface = None
self.start = Signal()
self.stop = Signal()
self.cnt_max = Signal(BV(self.width))
self.o = Signal()
-
+
def get_fragment(self):
comb = []
sync = []
def __init__(self,width=4,pipe=False):
self.width = width
self.pipe = pipe
+ self.interface = None
self.i = Signal(BV(self.width))
self._o = Signal()
self._mem = Memory(1, 2**self.width, self._lut_port, self._prog_port)
+ def write(self, truth_table):
+ for i in range(len(truth_table)):
+ val = truth_table[i]
+ we = 1<<17
+ dat = val<<16
+ addr = i
+ self.interface.write_n(self.reg_base, we + dat + addr,self.reg_size)
+ self.interface.write_n(self.reg_base, 0, self.reg_size)
+
def get_fragment(self):
comb = []
sync = []
return comb
class Trigger:
- def __init__(self,address, trig_width, dat_width, ports):
+ def __init__(self,address, trig_width, dat_width, ports, interface = None):
self.address = address
self.trig_width = trig_width
self.dat_width = dat_width
self.ports = ports
+ self.interface = interface
self.sum = Sum(len(self.ports))
self.in_trig = Signal(BV(self.trig_width))
port.reg_base = self.bank.get_base(port.reg_name)
self.sum.reg_base = self.bank.get_base(self.sum.reg_name)
+ # Update interface
+ for port in self.ports:
+ port.interface = self.interface
+ self.sum.interface = self.interface
+
def get_fragment(self):
comb = []
sync = []
self.d_width = d_width
self.max_burst = 8
# Csr interface
- self.csr = csr.Interface(self.d_width)
+ self.csr = csr.Interface(self.a_width, self.d_width)
# Spi interface
self.spi_clk = Signal()
self.spi_cs_n = Signal(reset=1)
import time
import serial
from struct import *
+from migen.fhdl.structure import *
def write_b(uart, data):
uart.write(pack('B',data))
read = self.uart.read()
if len(read) == 1:
break
- return read[0]
+ return int(read[0])
+
+ def read_n(self, addr, n, endianess = "LE"):
+ r = 0
+ words = int(2**bits_for(n-1)/8)
+ for i in range(words):
+ if endianess == "BE":
+ r += self.read(addr+i)<<(8*i)
+ elif endianess == "LE":
+ r += self.read(addr+words-1-i)<<(8*i)
+ return r
def write(self, addr, data):
write_b(self.uart, 0x01)
write_b(self.uart, (addr>>8)&0xFF)
write_b(self.uart, (addr&0xFF))
write_b(self.uart, data)
+ print("WR %02X @ %04X" %(data, addr))
+
+ def write_n(self, addr, data, n, endianess = "LE"):
+ words = int(2**bits_for(n-1)/8)
+ for i in range(words):
+ if endianess == "BE":
+ self.write(addr+i, (data>>(8*i)) & 0xFF)
+ elif endianess == "LE":
+ self.write(addr+words-1-i, (data>>(8*i)) & 0xFF)
+ print("WR %08X @ %04X" %(data, addr))
def main():
csr = Uart2Spi(1,115200)
projects / litex.git / commitdiff