add Rc to ternlogi

diff --git a/openpower/isa/bitmanip.mdwn b/openpower/isa/bitmanip.mdwn
index b2b0ad8b638d35ad966410d31365f963f5acbee8..d1521a762d1302f8a3c9502760d76fda8f711044 100644 (file)
--- a/openpower/isa/bitmanip.mdwn
+++ b/openpower/isa/bitmanip.mdwn
@@ -6,6 +6,7 @@
 TLI-Form
 
 * ternlogi RT, RA, RB, TLI
+* ternlogi. RT, RA, RB, TLI
 
 Pseudo-code:
 
@@ -17,7 +18,7 @@ Pseudo-code:
 
 Special Registers Altered:
 
-    None
+    CR0                    (if Rc=1)
 
 # Generalized Bit-Reverse
 

diff --git a/openpower/isatables/fields.text b/openpower/isatables/fields.text
index d4b5075f2b3c16252c6686163c0147d2546e1971..eb962688ca674db58b65100a159c1b20cfbbb886 100644 (file)
--- a/openpower/isatables/fields.text
+++ b/openpower/isatables/fields.text
@@ -288,8 +288,8 @@
    | PO   | SVme |mi0 | mi1 | mi2 | mo0 | mo1 |pst |///  | XO    | / |
 
 # 1.6.34 TLI-FORM
-   |0   |6   |11   |16   |21   |29  |
-   | PO | RT |  RA |  RB | TLI | XO |
+   |0   |6   |11   |16   |21   |29  |31 |
+   | PO | RT |  RA |  RB | TLI | XO |Rc |
 
 # 1.6.28 Instruction Fields
     A (6)
@@ -684,7 +684,7 @@
         1    Set Condition Register Field 0 or Field 1 as
              described in Section 2.3.1, 'Condition Regis-
              ter' on page 30.
-        Formats: A, M, MD, MDS, X, XFL, XO, XS, Z22, Z23, SVL, XB
+        Formats: A, M, MD, MDS, X, XFL, XO, XS, Z22, Z23, SVL, XB, TLI
     RIC (12:13)
         Field used to specify what types of entries to inval-
         idate for tlbie[l].

diff --git a/openpower/isatables/minor_5.csv b/openpower/isatables/minor_5.csv
index c0260dbf65e18ac3d4c1abe623becf5c77159810..071cc9995d75d977504b21811dab639d10954300 100644 (file)
--- a/openpower/isatables/minor_5.csv
+++ b/openpower/isatables/minor_5.csv
@@ -1,5 +1,5 @@
 opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form,CONDITIONS,unofficial,comment2
---------00-,SHIFT_ROT,OP_TERNLOG,RA,RB,RT,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,ternlogi,TLI,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+--------00-,SHIFT_ROT,OP_TERNLOG,RA,RB,RT,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,ternlogi,TLI,,1,unofficial until submitted and approved/renumbered by the opf isa wg
 0010010110-,SHIFT_ROT,OP_GREV,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,grev,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
 -011010110-,SHIFT_ROT,OP_GREV,RA,CONST_XBI,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,grevi,XB,,1,unofficial until submitted and approved/renumbered by the opf isa wg
 0010110110-,SHIFT_ROT,OP_GREV,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,grevw,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 8a0706309e18944bee87349f3cc46c38f4a3476f..afa3f76e44b1b07f6216a3d61a7a6ca46ba9dc63 100644 (file)
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -1268,8 +1268,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers):
             illegal = False
             ins_name = 'ffadds'
 
-        if asmop == 'ternlogi' \
-                or re.fullmatch(r'grevw?i?\.?', asmop or ''):
+        if re.fullmatch(r'ternlogi\.?|grevw?i?\.?', asmop or ''):
             illegal = False
             ins_name = asmop
 

diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py
index b43f317e19badc56b1f8e394babf8d3e16db96c7..26c2e2780643fad657964013d270d2d2b48e35c2 100644 (file)
--- a/src/openpower/decoder/power_decoder2.py
+++ b/src/openpower/decoder/power_decoder2.py
@@ -584,7 +584,7 @@ class DecodeOE(Elaboratable):
                         MicrOp.OP_SHL, MicrOp.OP_SHR, MicrOp.OP_RLC,
                         MicrOp.OP_LOAD, MicrOp.OP_STORE,
                         MicrOp.OP_RLCL, MicrOp.OP_RLCR,
-                        MicrOp.OP_EXTSWSLI, MicrOp.OP_GREV):
+                        MicrOp.OP_EXTSWSLI, MicrOp.OP_GREV, MicrOp.OP_TERNLOG):
                 pass
 
             # all other ops decode OE field

diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index 7b52769dd4cec7d3c4309cc20d7ffd4ee3f0955f..b1954160b493e54911c6451a94db8a5cef65e123 100644 (file)
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -283,20 +283,22 @@ class SVP64Asm:
 
         # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG
         # however we are out of space with opcode 22
-        if opcode == 'ternlogi':
+        if opcode in ('ternlogi', 'ternlogi.'):
             po = 5
             xo = 0
             rt = int(fields[0])
             ra = int(fields[1])
             rb = int(fields[2])
             imm = int(fields[3])
+            rc = '.' in opcode
             instr = po
             instr = (instr << 5) | rt
             instr = (instr << 5) | ra
             instr = (instr << 5) | rb
             instr = (instr << 8) | imm
-            instr = (instr << 3) | xo
-            asm = f"ternlogi {rt}, {ra}, {rb}, {imm}"
+            instr = (instr << 2) | xo
+            instr = (instr << 1) | rc
+            asm = f"{opcode} {rt}, {ra}, {rb}, {imm}"
             yield f".4byte {hex(instr)} # {asm}"
             return
 

diff --git a/src/openpower/test/bitmanip/bitmanip_cases.py b/src/openpower/test/bitmanip/bitmanip_cases.py
index 0fcb0d7139e33fdf3fd84851f6877ff925b5a084..88bdd057e8545f62f9b03ffa5f6f7c2edb833b80 100644 (file)
--- a/src/openpower/test/bitmanip/bitmanip_cases.py
+++ b/src/openpower/test/bitmanip/bitmanip_cases.py
@@ -7,8 +7,9 @@ from nmutil.sim_util import hash_256
 
 
 class BitManipTestCase(TestAccumulatorBase):
-    def do_case_ternlogi(self, rt, ra, rb, imm):
-        lst = [f"ternlogi 3, 4, 5, {imm}"]
+    def do_case_ternlogi(self, rc, rt, ra, rb, imm):
+        rc_dot = "." if rc else ""
+        lst = [f"ternlogi{rc_dot} 3, 4, 5, {imm}"]
         initial_regs = [0] * 32
         rt %= 2 ** 64
         ra %= 2 ** 64
@@ -32,6 +33,13 @@ class BitManipTestCase(TestAccumulatorBase):
         e.intregs[3] = expected
         e.intregs[4] = ra
         e.intregs[5] = rb
+        if rc:
+            if expected & 2 ** 63:  # sign extend
+                expected -= 2 ** 64
+            eq = expected == 0
+            gt = expected > 0
+            lt = expected < 0
+            e.crregs[0] = (eq << 1) | (gt << 2) | (lt << 3)
         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 
     def do_case_grev(self, w, is_imm, ra, rb):
@@ -65,20 +73,27 @@ class BitManipTestCase(TestAccumulatorBase):
         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 
     def case_ternlogi_0(self):
-        self.do_case_ternlogi(0x8000_0000_FFFF_0000,
+        self.do_case_ternlogi(False,
+                              0x8000_0000_FFFF_0000,
+                              0x8000_0000_FF00_FF00,
+                              0x8000_0000_F0F0_F0F0, 0x80)
+        self.do_case_ternlogi(True,
+                              0x8000_0000_FFFF_0000,
                               0x8000_0000_FF00_FF00,
                               0x8000_0000_F0F0_F0F0, 0x80)
 
     def case_ternlogi_FF(self):
-        self.do_case_ternlogi(0, 0, 0, 0xFF)
+        self.do_case_ternlogi(False, 0, 0, 0, 0xFF)
+        self.do_case_ternlogi(True, 0, 0, 0, 0xFF)
 
     def case_ternlogi_random(self):
         for i in range(100):
+            rc = bool(hash_256(f"ternlogi rc {i}") & 1)
             imm = hash_256(f"ternlogi imm {i}") & 0xFF
             rt = hash_256(f"ternlogi rt {i}") % 2 ** 64
             ra = hash_256(f"ternlogi ra {i}") % 2 ** 64
             rb = hash_256(f"ternlogi rb {i}") % 2 ** 64
-            self.do_case_ternlogi(rt, ra, rb, imm)
+            self.do_case_ternlogi(rc, rt, ra, rb, imm)
 
     def case_grev_random(self):
         for i in range(100):