dict<SigBit, bool> init_map;
pool<SigBit> input_bits, output_bits;
- dict<SigBit, SigBit> not_map, ff_map, alias_map;
+ dict<SigBit, SigBit> not_map, /*ff_map,*/ alias_map;
dict<SigBit, pair<SigBit, SigBit>> and_map;
vector<std::tuple<SigBit,RTLIL::Cell*,RTLIL::IdString,int>> ci_bits;
vector<std::tuple<SigBit,RTLIL::Cell*,RTLIL::IdString,int,int>> co_bits;
- vector<std::pair<SigBit,int>> ff_bits;
+ dict<SigBit, int> ff_bits;
dict<SigBit, float> arrival_times;
vector<pair<int, int>> aig_gates;
// box ordering, but not individual AIG cells
dict<SigBit, pool<IdString>> bit_drivers, bit_users;
TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
- struct flop_data_t {
- IdString d_port;
- IdString q_port;
- int q_arrival;
- };
- dict<IdString, flop_data_t> flop_data;
bool abc_box_seen = false;
+ std::vector<Cell*> flop_boxes;
for (auto cell : module->selected_cells()) {
if (cell->type == "$_NOT_")
unused_bits.erase(D);
undriven_bits.erase(Q);
alias_map[Q] = D;
+ auto r = ff_bits.insert(std::make_pair(D, 0));
+ log_assert(r.second);
continue;
}
toposort.node(cell->name);
- auto r = flop_data.insert(std::make_pair(cell->type, flop_data_t{IdString(), IdString(), 0}));
- if (r.second && inst_module->attributes.count("\\abc_flop")) {
- IdString &abc_flop_d = r.first->second.d_port;
- IdString &abc_flop_q = r.first->second.q_port;
- for (auto port_name : inst_module->ports) {
- auto wire = inst_module->wire(port_name);
- log_assert(wire);
- if (wire->attributes.count("\\abc_flop_d")) {
- if (abc_flop_d != IdString())
- log_error("More than one port has the 'abc_flop_d' attribute set on module '%s'.\n", log_id(cell->type));
- abc_flop_d = port_name;
- }
- if (wire->attributes.count("\\abc_flop_q")) {
- if (abc_flop_q != IdString())
- log_error("More than one port has the 'abc_flop_q' attribute set on module '%s'.\n", log_id(cell->type));
- abc_flop_q = port_name;
-
- auto it = wire->attributes.find("\\abc_arrival");
- if (it != wire->attributes.end()) {
- if (it->second.flags != 0)
- log_error("Attribute 'abc_arrival' on port '%s' of module '%s' is not an integer.\n", log_id(wire), log_id(cell->type));
- r.first->second.q_arrival = it->second.as_int();
- }
- }
- }
- if (abc_flop_d == IdString())
- log_error("'abc_flop_d' attribute not found on any ports on module '%s'.\n", log_id(cell->type));
- if (abc_flop_q == IdString())
- log_error("'abc_flop_q' attribute not found on any ports on module '%s'.\n", log_id(cell->type));
- }
-
- auto abc_flop_d = r.first->second.d_port;
- if (abc_flop_d != IdString()) {
- SigBit d = cell->getPort(abc_flop_d);
- SigBit I = sigmap(d);
- if (I != d)
- alias_map[d] = I;
- unused_bits.erase(d);
-
- auto abc_flop_q = r.first->second.q_port;
- SigBit q = cell->getPort(abc_flop_q);
- log_assert(q == sigmap(q));
- undriven_bits.erase(q);
- auto it = cell->attributes.find(ID(abc_mergeability));
- log_assert(it != cell->attributes.end());
- ff_bits.emplace_back(q, it->second.as_int());
- cell->attributes.erase(it);
-
- auto arrival = r.first->second.q_arrival;
- if (arrival)
- arrival_times[q] = arrival;
- }
-
for (const auto &conn : cell->connections()) {
auto port_wire = inst_module->wire(conn.first);
if (port_wire->port_input) {
bit_drivers[bit].insert(cell->name);
}
+ if (inst_module->attributes.count("\\abc9_flop"))
+ flop_boxes.push_back(cell);
continue;
}
}
if (abc_box_seen) {
+ dict<IdString, std::pair<IdString,int>> flop_q;
+ for (auto cell : flop_boxes) {
+ auto r = flop_q.insert(std::make_pair(cell->type, std::make_pair(IdString(), 0)));
+ SigBit d;
+ if (r.second) {
+ for (const auto &conn : cell->connections()) {
+ const SigSpec &rhs = conn.second;
+ if (!rhs.is_bit())
+ continue;
+ if (!ff_bits.count(rhs))
+ continue;
+ r.first->second.first = conn.first;
+ Module *inst_module = module->design->module(cell->type);
+ Wire *wire = inst_module->wire(conn.first);
+ log_assert(wire);
+ auto jt = wire->attributes.find("\\abc_arrival");
+ if (jt != wire->attributes.end()) {
+ if (jt->second.flags != 0)
+ log_error("Attribute 'abc_arrival' on port '%s' of module '%s' is not an integer.\n", log_id(wire), log_id(cell->type));
+ r.first->second.second = jt->second.as_int();
+ }
+ d = rhs;
+ log_assert(d == sigmap(d));
+ break;
+ }
+ }
+ else
+ d = cell->getPort(r.first->second.first);
+
+ auto it = cell->attributes.find(ID(abc9_mergeability));
+ log_assert(it != cell->attributes.end());
+ ff_bits.at(d) = it->second.as_int();
+ cell->attributes.erase(it);
+
+ auto arrival = r.first->second.second;
+ if (arrival)
+ arrival_times[d] = arrival;
+ }
+
for (auto &it : bit_users)
if (bit_drivers.count(it.first))
for (auto driver_cell : bit_drivers.at(it.first))
}
}
}
+
+ if (box_module->get_bool_attribute("\\abc9_flop")) {
+ IdString port_name = "\\$currQ";
+ RTLIL::Wire* w = box_module->wire(port_name);
+ SigSpec rhs = cell->getPort(port_name);
+ log_assert(GetSize(w) == GetSize(rhs));
+
+ int offset = 0;
+ for (auto b : rhs.bits()) {
+ SigBit I = sigmap(b);
+ if (b == RTLIL::Sx)
+ b = State::S0;
+ else if (I != b) {
+ if (I == RTLIL::Sx)
+ alias_map[b] = State::S0;
+ else
+ alias_map[b] = I;
+ }
+ co_bits.emplace_back(b, cell, port_name, offset++, 0);
+ unused_bits.erase(b);
+ }
+ }
+
box_list.emplace_back(cell);
}
}
not_map.sort();
- ff_map.sort();
+ //ff_map.sort();
and_map.sort();
aig_map[State::S0] = 0;
}
}
+ if (box_module->get_bool_attribute("\\abc9_flop")) {
+ log_assert(holes_cell);
+ IdString port_name = "\\$currQ";
+ Wire* w = box_module->wire(port_name);
+ SigSpec rhs = cell->getPort(port_name);
+ log_assert(GetSize(w) == GetSize(rhs));
+ SigSpec port_wire;
+ Wire *holes_wire;
+ for (int i = 0; i < GetSize(w); i++) {
+ box_inputs++;
+ holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
+ if (!holes_wire) {
+ holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
+ holes_wire->port_input = true;
+ holes_wire->port_id = port_id++;
+ holes_module->ports.push_back(holes_wire->name);
+ }
+ port_wire.append(holes_wire);
+ }
+ holes_cell->setPort(w->name, port_wire);
+ }
+
write_h_buffer(box_inputs);
write_h_buffer(box_outputs);
write_h_buffer(box_module->attributes.at("\\abc_box_id").as_int());
log_debug("flopNum = %d\n", GetSize(ff_bits));
write_r_buffer(ff_bits.size());
for (const auto &i : ff_bits) {
+ log_assert(i.second > 0);
write_r_buffer(i.second);
const SigBit &bit = i.first;
write_i_buffer(arrival_times.at(bit, 0));
bool is_flop = false;
if (seen_boxes.insert(cell->type).second) {
- if (box_module->attributes.count("\\abc_flop")) {
+ if (box_module->attributes.count("\\abc9_flop")) {
log_assert(flop_count < flopNum);
flops.insert(cell->type);
is_flop = true;
}
rhs.append(wire);
}
-
- if (!is_flop || port_name != "\\$pastQ")
- cell->setPort(port_name, rhs);
+ cell->setPort(port_name, rhs);
}
if (is_flop) {
+ Wire* port = box_module->wire("\\$currQ");
+ log_assert(port);
+ log_assert(co_count < outputs.size());
+ Wire *wire = outputs[co_count++];
+ log_assert(wire);
+ log_assert(wire->port_output);
+ wire->port_output = false;
+
RTLIL::Wire *d = outputs[outputs.size() - flopNum + flop_count];
log_assert(d);
log_assert(d->port_output);
log_assert(q->port_input);
q->port_input = false;
+ auto ff = module->addCell(NEW_ID, "$__ABC_FF_");
+ ff->setPort("\\D", d);
+ ff->setPort("\\Q", q);
flop_count++;
- module->connect(q, d);
- cell->set_bool_attribute("\\abc_flop");
continue;
}
}
cell_stats[mapped_cell->type]++;
RTLIL::Cell *existing_cell = nullptr;
- if (mapped_cell->type == ID($lut)) {
- if (GetSize(mapped_cell->getPort(ID::A)) == 1 && mapped_cell->getParam(ID(LUT)) == RTLIL::Const::from_string("01")) {
+ if (mapped_cell->type.in(ID($lut), ID($__ABC_FF_))) {
+ if (mapped_cell->type == ID($lut) &&
+ GetSize(mapped_cell->getPort(ID::A)) == 1 &&
+ mapped_cell->getParam(ID(LUT)) == RTLIL::Const::from_string("01")) {
SigSpec my_a = module->wires_.at(remap_name(mapped_cell->getPort(ID::A).as_wire()->name));
SigSpec my_y = module->wires_.at(remap_name(mapped_cell->getPort(ID::Y).as_wire()->name));
module->connect(my_y, my_a);
cell->attributes = mapped_cell->attributes;
}
- auto abc_flop = mapped_cell->attributes.count("\\abc_flop");
+ RTLIL::Module* box_module = design->module(mapped_cell->type);
+ auto abc_flop = box_module && box_module->attributes.count("\\abc9_flop");
for (auto &conn : mapped_cell->connections()) {
RTLIL::SigSpec newsig;
for (auto c : conn.second.chunks()) {
std::set<RTLIL::Cell*> expand_queue_up, next_expand_queue_up;
std::set<RTLIL::Cell*> expand_queue_down, next_expand_queue_down;
- typedef pair<bool, RTLIL::SigSpec> clkdomain_t;
- std::map<clkdomain_t, pool<RTLIL::IdString>> assigned_cells;
- std::map<RTLIL::Cell*, clkdomain_t> assigned_cells_reverse;
+ std::map<SigSpec, pool<RTLIL::IdString>> assigned_cells;
+ std::map<RTLIL::Cell*, SigSpec> assigned_cells_reverse;
std::map<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_bit, cell_to_bit_up, cell_to_bit_down;
std::map<RTLIL::SigBit, std::set<RTLIL::Cell*>> bit_to_cell, bit_to_cell_up, bit_to_cell_down;
- pool<IdString> seen_cells;
- struct flop_data_t {
- IdString clk_port;
- IdString en_port;
- };
- dict<IdString, flop_data_t> flop_data;
- typedef clkdomain_t endomain_t;
+ typedef std::pair<IdString, SigSpec> endomain_t;
std::map<endomain_t, int> mergeability_class;
for (auto cell : all_cells) {
- clkdomain_t key;
- endomain_t key2;
-
for (auto &conn : cell->connections())
- for (auto bit : conn.second) {
- bit = assign_map(bit);
+ for (auto bit : assign_map(conn.second))
if (bit.wire != nullptr) {
cell_to_bit[cell].insert(bit);
bit_to_cell[bit].insert(cell);
bit_to_cell_up[bit].insert(cell);
}
}
- }
-
- // TODO: Generate this outside
- decltype(flop_data)::iterator it;
- if (seen_cells.insert(cell->type).second) {
- RTLIL::Module* inst_module = design->module(cell->type);
- if (!inst_module)
- continue;
-
- if (!inst_module->attributes.count("\\abc_flop"))
- continue;
-
- IdString abc_flop_clk, abc_flop_en;
- for (auto port_name : inst_module->ports) {
- auto wire = inst_module->wire(port_name);
- log_assert(wire);
- if (wire->attributes.count("\\abc_flop_clk")) {
- if (abc_flop_clk != IdString())
- log_error("More than one port has the 'abc_flop_clk' attribute set on module '%s'.\n", log_id(cell->type));
- abc_flop_clk = port_name;
- }
- if (wire->attributes.count("\\abc_flop_en")) {
- if (abc_flop_en != IdString())
- log_error("More than one port has the 'abc_flop_en' attribute set on module '%s'.\n", log_id(cell->type));
- abc_flop_en = port_name;
- }
- }
- if (abc_flop_clk == IdString())
- log_error("'abc_flop_clk' attribute not found on any ports on module '%s'.\n", log_id(cell->type));
- if (abc_flop_en == IdString())
- log_error("'abc_flop_en' attribute not found on any ports on module '%s'.\n", log_id(cell->type));
+ auto inst_module = design->module(cell->type);
+ if (!inst_module || !inst_module->attributes.count("\\abc9_flop"))
+ continue;
- it = flop_data.insert(std::make_pair(cell->type, flop_data_t{abc_flop_clk, abc_flop_en})).first;
- }
- else {
- it = flop_data.find(cell->type);
- if (it == flop_data.end())
- continue;
+ auto derived_name = inst_module->derive(design, cell->parameters);
+ auto derived_module = design->module(derived_name);
+ log_assert(derived_module);
+ Pass::call_on_module(design, derived_module, "proc");
+ SigMap derived_sigmap(derived_module);
+
+ Wire *currQ = derived_module->wire("\\$currQ");
+ if (currQ == NULL)
+ log_error("'\\$currQ' is not a wire present in module '%s'.\n", log_id(cell->type));
+ log_assert(!currQ->port_output);
+ if (!currQ->port_input) {
+ currQ->port_input = true;
+ derived_module->ports.push_back(currQ->name);
+ currQ->port_id = GetSize(derived_module->ports);
+#ifndef NDEBUG
+ derived_module->check();
+#endif
}
- const auto &data = it->second;
-
- auto jt = cell->parameters.find("\\CLK_POLARITY");
- if (jt == cell->parameters.end())
- log_error("'CLK_POLARITY' is not a parameter on module '%s'.\n", log_id(cell->type));
- bool this_clk_pol = jt->second.as_bool();
-
- jt = cell->parameters.find("\\EN_POLARITY");
- if (jt == cell->parameters.end())
- log_error("'EN_POLARITY' is not a parameter on module '%s'.\n", log_id(cell->type));
- bool this_en_pol = jt->second.as_bool();
+ SigSpec pattern;
+ SigSpec with;
+ for (auto &conn : cell->connections()) {
+ Wire *first = derived_module->wire(conn.first);
+ log_assert(first);
+ SigSpec second = assign_map(conn.second);
+ log_assert(GetSize(first) == GetSize(second));
+ pattern.append(first);
+ with.append(second);
+ }
- key = clkdomain_t(this_clk_pol, assign_map(cell->getPort(data.clk_port)));
+ Wire *abc9_clock_wire = derived_module->wire("\\$abc9_clock");
+ if (abc9_clock_wire == NULL)
+ log_error("'\\$abc9_clock' is not a wire present in module '%s'.\n", log_id(cell->type));
+ SigSpec abc9_clock = derived_sigmap(abc9_clock_wire);
+ abc9_clock.replace(pattern, with);
+ for (const auto &c : abc9_clock.chunks())
+ log_assert(!c.wire || c.wire->module == mod);
+
+ Wire *abc9_control_wire = derived_module->wire("\\$abc9_control");
+ if (abc9_control_wire == NULL)
+ log_error("'\\$abc9_control' is not a wire present in module '%s'.\n", log_id(cell->type));
+ SigSpec abc9_control = derived_sigmap(abc9_control_wire);
+ abc9_control.replace(pattern, with);
+ for (const auto &c : abc9_control.chunks())
+ log_assert(!c.wire || c.wire->module == mod);
unassigned_cells.erase(cell);
expand_queue.insert(cell);
expand_queue_up.insert(cell);
expand_queue_down.insert(cell);
- assigned_cells[key].insert(cell->name);
- assigned_cells_reverse[cell] = key;
+ assigned_cells[abc9_clock].insert(cell->name);
+ assigned_cells_reverse[cell] = abc9_clock;
- key2 = endomain_t(this_en_pol, assign_map(cell->getPort(data.en_port)));
- auto r = mergeability_class.emplace(key2, mergeability_class.size() + 1);
- auto YS_ATTRIBUTE(unused) r2 = cell->attributes.insert(std::make_pair(ID(abc_mergeability), r.first->second));
+ endomain_t key(cell->type, abc9_control);
+ auto r = mergeability_class.emplace(key, mergeability_class.size() + 1);
+ auto YS_ATTRIBUTE(unused) r2 = cell->attributes.insert(std::make_pair(ID(abc9_mergeability), r.first->second));
log_assert(r2.second);
}
if (!expand_queue_up.empty())
{
RTLIL::Cell *cell = *expand_queue_up.begin();
- clkdomain_t key = assigned_cells_reverse.at(cell);
+ SigSpec key = assigned_cells_reverse.at(cell);
expand_queue_up.erase(cell);
for (auto bit : cell_to_bit_up[cell])
if (!expand_queue_down.empty())
{
RTLIL::Cell *cell = *expand_queue_down.begin();
- clkdomain_t key = assigned_cells_reverse.at(cell);
+ SigSpec key = assigned_cells_reverse.at(cell);
expand_queue_down.erase(cell);
for (auto bit : cell_to_bit_down[cell])
while (!expand_queue.empty())
{
RTLIL::Cell *cell = *expand_queue.begin();
- clkdomain_t key = assigned_cells_reverse.at(cell);
+ SigSpec key = assigned_cells_reverse.at(cell);
expand_queue.erase(cell);
for (auto bit : cell_to_bit.at(cell)) {
expand_queue.swap(next_expand_queue);
}
- clkdomain_t key(true, RTLIL::SigSpec());
+ SigSpec key;
for (auto cell : unassigned_cells) {
assigned_cells[key].insert(cell->name);
assigned_cells_reverse[cell] = key;
log_header(design, "Summary of detected clock domains:\n");
for (auto &it : assigned_cells)
- log(" %d cells in clk=%s%s\n", GetSize(it.second),
- std::get<0>(it.first) ? "" : "!", log_signal(std::get<1>(it.first)));
+ log(" %d cells in clk=%s\n", GetSize(it.second), log_signal(it.first));
design->selection_stack.emplace_back(false);
for (auto &it : assigned_cells) {
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_R_INVERTED = 1'b0;
wire \$nextQ ;
- \$__ABC_FDRE #(
+ FDRE #(
.INIT(INIT),
.IS_C_INVERTED(IS_C_INVERTED),
.IS_D_INVERTED(IS_D_INVERTED),
- .IS_R_INVERTED(IS_R_INVERTED),
- .CLK_POLARITY(!IS_C_INVERTED),
- .EN_POLARITY(1'b1)
+ .IS_R_INVERTED(IS_R_INVERTED)
) _TECHMAP_REPLACE_ (
- .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .R(R)
+ .D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .R(R)
);
\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
endmodule
module FDRE_1 (output reg Q, input C, CE, D, R);
parameter [0:0] INIT = 1'b0;
wire \$nextQ ;
- \$__ABC_FDRE_1 #(
- .INIT(|0),
- .CLK_POLARITY(1'b0),
- .EN_POLARITY(1'b1)
+ FDRE_1 #(
+ .INIT(|0),
) _TECHMAP_REPLACE_ (
- .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .R(R)
+ .D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .R(R)
);
\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
endmodule
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_CLR_INVERTED = 1'b0;
wire \$nextQ , \$currQ ;
- \$__ABC_FDCE #(
+ FDCE #(
.INIT(INIT),
.IS_C_INVERTED(IS_C_INVERTED),
.IS_D_INVERTED(IS_D_INVERTED),
- .IS_CLR_INVERTED(IS_CLR_INVERTED),
- .CLK_POLARITY(!IS_C_INVERTED),
- .EN_POLARITY(1'b1)
+ .IS_CLR_INVERTED(IS_CLR_INVERTED)
) _TECHMAP_REPLACE_ (
- .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR)
+ .D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .CLR(CLR)
);
\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
- \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(CLR), .Y(Q));
+ \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(CLR ^ IS_CLR_INVERTED), .Y(Q));
endmodule
module FDCE_1 (output reg Q, input C, CE, D, CLR);
parameter [0:0] INIT = 1'b0;
wire \$nextQ , \$currQ ;
- \$__ABC_FDCE_1 #(
- .INIT(INIT),
- .CLK_POLARITY(1'b0),
- .EN_POLARITY(1'b1)
+ FDCE_1 #(
+ .INIT(INIT)
) _TECHMAP_REPLACE_ (
- .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR)
+ .D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .CLR(CLR)
);
\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
\$__ABC_ASYNC abc_async (.A(\$currQ ), .S(CLR), .Y(Q));
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_PRE_INVERTED = 1'b0;
wire \$nextQ , \$currQ ;
- \$__ABC_FDPE #(
+ FDPE #(
.INIT(INIT),
.IS_C_INVERTED(IS_C_INVERTED),
.IS_D_INVERTED(IS_D_INVERTED),
.IS_PRE_INVERTED(IS_PRE_INVERTED),
- .CLK_POLARITY(!IS_C_INVERTED),
- .EN_POLARITY(1'b1)
) _TECHMAP_REPLACE_ (
- .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE)
+ .D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .PRE(PRE)
);
\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
- \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(PRE), .Y(Q));
+ \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(PRE ^ IS_PRE_INVERTED), .Y(Q));
endmodule
module FDPE_1 (output reg Q, input C, CE, D, PRE);
parameter [0:0] INIT = 1'b0;
wire \$nextQ , \$currQ ;
- \$__ABC_FDPE_1 #(
- .INIT(INIT),
- .CLK_POLARITY(1'b0),
- .EN_POLARITY(1'b1)
+ FDPE_1 #(
+ .INIT(INIT)
) _TECHMAP_REPLACE_ (
- .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE)
+ .D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .PRE(PRE)
);
\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
\$__ABC_ASYNC abc_async (.A(\$currQ ), .S(PRE), .Y(Q));
endmodule
+module FDSE (output reg Q, input C, CE, D, S);
+ parameter [0:0] INIT = 1'b0;
+ parameter [0:0] IS_C_INVERTED = 1'b0;
+ parameter [0:0] IS_D_INVERTED = 1'b0;
+ parameter [0:0] IS_S_INVERTED = 1'b0;
+ wire \$nextQ ;
+ FDSE #(
+ .INIT(INIT),
+ .IS_C_INVERTED(IS_C_INVERTED),
+ .IS_D_INVERTED(IS_D_INVERTED),
+ .IS_S_INVERTED(IS_S_INVERTED)
+ ) _TECHMAP_REPLACE_ (
+ .D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .S(S)
+ );
+ \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
+endmodule
+module FDSE_1 (output reg Q, input C, CE, D, S);
+ parameter [0:0] INIT = 1'b0;
+ wire \$nextQ ;
+ FDSE_1 #(
+ .INIT(|0),
+ ) _TECHMAP_REPLACE_ (
+ .D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .S(S)
+ );
+ \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
+endmodule
+
module RAM32X1D (
output DPO, SPO,
input D,
: (S0 ? I1 : I0);
endmodule
-module \$__ABC_FF_ (input C, D, output Q);
+module \$__ABC_FF_ (input D, output Q);
endmodule
(* abc_box_id = 1000 *)
module \$__ABC_ASYNC (input A, S, output Y);
endmodule
-
-(* abc_box_id=1001, lib_whitebox, abc_flop *)
-module \$__ABC_FDRE ((* abc_flop_q, abc_arrival=303 *) output Q,
- (* abc_flop_clk *) input C,
- (* abc_flop_en *) input CE,
- (* abc_flop_d *) input D,
- input R, \$pastQ );
- parameter [0:0] INIT = 1'b0;
- parameter [0:0] IS_C_INVERTED = 1'b0;
- parameter [0:0] IS_D_INVERTED = 1'b0;
- parameter [0:0] IS_R_INVERTED = 1'b0;
- parameter CLK_POLARITY = !IS_C_INVERTED;
- parameter EN_POLARITY = 1'b1;
- assign Q = (R ^ IS_R_INVERTED) ? 1'b0 : (CE ? (D ^ IS_D_INVERTED) : \$pastQ );
-endmodule
-
-(* abc_box_id=1002, lib_whitebox, abc_flop *)
-module \$__ABC_FDRE_1 ((* abc_flop_q, abc_arrival=303 *) output Q,
- (* abc_flop_clk *) input C,
- (* abc_flop_en *) input CE,
- (* abc_flop_d *) input D,
- input R, \$pastQ );
- parameter [0:0] INIT = 1'b0;
- parameter CLK_POLARITY = 1'b0;
- parameter EN_POLARITY = 1'b1;
- assign Q = R ? 1'b0 : (CE ? D : \$pastQ );
-endmodule
-
-(* abc_box_id=1003, lib_whitebox, abc_flop *)
-module \$__ABC_FDCE ((* abc_flop_q, abc_arrival=303 *) output Q,
- (* abc_flop_clk *) input C,
- (* abc_flop_en *) input CE,
- (* abc_flop_d *) input D,
- input CLR, \$pastQ );
- parameter [0:0] INIT = 1'b0;
- parameter [0:0] IS_C_INVERTED = 1'b0;
- parameter [0:0] IS_D_INVERTED = 1'b0;
- parameter [0:0] IS_CLR_INVERTED = 1'b0;
- parameter CLK_POLARITY = !IS_C_INVERTED;
- parameter EN_POLARITY = 1'b1;
- assign Q = (CE && !(CLR ^ IS_CLR_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
-endmodule
-
-(* abc_box_id=1004, lib_whitebox, abc_flop *)
-module \$__ABC_FDCE_1 ((* abc_flop_q, abc_arrival=303 *) output Q,
- (* abc_flop_clk *) input C,
- (* abc_flop_en *) input CE,
- (* abc_flop_d *) input D,
- input CLR, \$pastQ );
- parameter [0:0] INIT = 1'b0;
- parameter CLK_POLARITY = 1'b0;
- parameter EN_POLARITY = 1'b1;
- assign Q = (CE && !CLR) ? D : \$pastQ ;
-endmodule
-
-(* abc_box_id=1005, lib_whitebox, abc_flop *)
-module \$__ABC_FDPE ((* abc_flop_q, abc_arrival=303 *) output Q,
- (* abc_flop_clk *) input C,
- (* abc_flop_en *) input CE,
- (* abc_flop_d *) input D,
- input PRE, \$pastQ );
- parameter [0:0] INIT = 1'b0;
- parameter [0:0] IS_C_INVERTED = 1'b0;
- parameter [0:0] IS_D_INVERTED = 1'b0;
- parameter [0:0] IS_PRE_INVERTED = 1'b0;
- parameter CLK_POLARITY = !IS_C_INVERTED;
- parameter EN_POLARITY = 1'b1;
- assign Q = (CE && !(PRE ^ IS_PRE_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
-endmodule
-
-(* abc_box_id=1006, lib_whitebox, abc_flop *)
-module \$__ABC_FDPE_1 ((* abc_flop_q, abc_arrival=303 *) output Q,
- (* abc_flop_clk *) input C,
- (* abc_flop_en *) input CE,
- (* abc_flop_d *) input D,
- input PRE, \$pastQ );
- parameter [0:0] INIT = 1'b0;
- parameter CLK_POLARITY = 1'b0;
- parameter EN_POLARITY = 1'b1;
- assign Q = (CE && !PRE) ? D : \$pastQ ;
-endmodule
-
-(* abc_box_id=2000 *)
-module \$__ABC_LUT6 (input A, input [5:0] S, output Y);
-endmodule
-(* abc_box_id=2001 *)
-module \$__ABC_LUT7 (input A, input [6:0] S, output Y);
-endmodule
assign Y = A;
endmodule
-module \$__ABC_FDRE (output Q,
- input C,
- input CE,
- input D,
- input R, \$pastQ );
- parameter [0:0] INIT = 1'b0;
- parameter [0:0] IS_C_INVERTED = 1'b0;
- parameter [0:0] IS_D_INVERTED = 1'b0;
- parameter [0:0] IS_R_INVERTED = 1'b0;
- parameter CLK_POLARITY = !IS_C_INVERTED;
- parameter EN_POLARITY = 1'b1;
-
- FDRE #(
- .INIT(INIT),
- .IS_C_INVERTED(IS_C_INVERTED),
- .IS_D_INVERTED(IS_D_INVERTED),
- .IS_R_INVERTED(IS_R_INVERTED),
- ) _TECHMAP_REPLACE_ (
- .D(D), .Q(Q), .C(C), .CE(CE), .R(R)
- );
-endmodule
-
-module \$__ABC_FDRE_1 (output Q,
- input C,
- input CE,
- input D,
- input R, \$pastQ );
- parameter [0:0] INIT = 1'b0;
- parameter CLK_POLARITY = 1'b0;
- parameter EN_POLARITY = 1'b1;
- assign Q = R ? 1'b0 : (CE ? D : \$pastQ );
-
- FDRE_1 #(
- .INIT(INIT),
- ) _TECHMAP_REPLACE_ (
- .D(D), .Q(Q), .C(C), .CE(CE), .R(R)
- );
-endmodule
-
-module \$__ABC_FDCE (output Q,
- input C,
- input CE,
- input D,
- input CLR, \$pastQ );
- parameter [0:0] INIT = 1'b0;
- parameter [0:0] IS_C_INVERTED = 1'b0;
- parameter [0:0] IS_D_INVERTED = 1'b0;
- parameter [0:0] IS_CLR_INVERTED = 1'b0;
- parameter CLK_POLARITY = !IS_C_INVERTED;
- parameter EN_POLARITY = 1'b1;
-
- FDCE #(
- .INIT(INIT),
- .IS_C_INVERTED(IS_C_INVERTED),
- .IS_D_INVERTED(IS_D_INVERTED),
- .IS_CLR_INVERTED(IS_CLR_INVERTED),
- ) _TECHMAP_REPLACE_ (
- .D(D), .Q(Q), .C(C), .CE(CE), .CLR(CLR)
- );
-endmodule
-
-module \$__ABC_FDCE_1 (output Q,
- input C,
- input CE,
- input D,
- input CLR, \$pastQ );
- parameter [0:0] INIT = 1'b0;
- parameter CLK_POLARITY = 1'b0;
- parameter EN_POLARITY = 1'b1;
-
- FDCE_1 #(
- .INIT(INIT),
- ) _TECHMAP_REPLACE_ (
- .D(D), .Q(Q), .C(C), .CE(CE), .CLR(CLR)
- );
-endmodule
-
-module \$__ABC_FDPE (output Q,
- input C,
- input CE,
- input D,
- input PRE, \$pastQ );
- parameter [0:0] INIT = 1'b0;
- parameter [0:0] IS_C_INVERTED = 1'b0;
- parameter [0:0] IS_D_INVERTED = 1'b0;
- parameter [0:0] IS_PRE_INVERTED = 1'b0;
- parameter CLK_POLARITY = !IS_C_INVERTED;
- parameter EN_POLARITY = 1'b1;
-
- FDPE #(
- .INIT(INIT),
- .IS_C_INVERTED(IS_C_INVERTED),
- .IS_D_INVERTED(IS_D_INVERTED),
- .IS_PRE_INVERTED(IS_PRE_INVERTED),
- ) _TECHMAP_REPLACE_ (
- .D(D), .Q(Q), .C(C), .CE(CE), .PRE(PRE)
- );
-endmodule
-
-module \$__ABC_FDPE_1 (output Q,
- input C,
- input CE,
- input D,
- input PRE, \$pastQ );
- parameter [0:0] INIT = 1'b0;
- parameter CLK_POLARITY = 1'b0;
- parameter EN_POLARITY = 1'b1;
-
- FDPE_1 #(
- .INIT(INIT),
- ) _TECHMAP_REPLACE_ (
- .D(D), .Q(Q), .C(C), .CE(CE), .PRE(PRE)
- );
-endmodule
-
-module \$__ABC_LUT6 (input A, input [5:0] S, output Y);
- assign Y = A;
-endmodule
-module \$__ABC_LUT7 (input A, input [6:0] S, output Y);
- assign Y = A;
+module \$__ABC_FF_ (input D, output Q);
+ assign Q = D;
endmodule
# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L237-L251
# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L265-L277
-# Inputs: C CE D R \$pastQ
+# Inputs: C CE D R \$currQ
# Outputs: Q
FDRE 1001 1 5 1
0 151 0 446 0
-# Inputs: C CE D R \$pastQ
+# Inputs: C CE D R \$currQ
# Outputs: Q
FDRE_1 1002 1 5 1
0 151 0 446 0
-# Inputs: C CE CLR D \$pastQ
+# Inputs: C CE CLR D \$currQ
# Outputs: Q
FDCE 1003 1 5 1
0 151 806 0 0
-# Inputs: C CE CLR D \$pastQ
+# Inputs: C CE CLR D \$currQ
# Outputs: Q
FDCE_1 1004 1 5 1
0 151 806 0 0
-# Inputs: C CE D PRE \$pastQ
+# Inputs: C CE D PRE \$currQ
# Outputs: Q
FDPE 1005 1 5 1
0 151 0 806 0
-# Inputs: C CE D PRE \$pastQ
+# Inputs: C CE D PRE \$currQ
# Outputs: Q
FDPE_1 1006 1 5 1
0 151 0 806 0
+# Inputs: C CE D S \$currQ
+# Outputs: Q
+FDSE 1007 1 5 1
+0 151 0 446 0
+
+# Inputs: C CE D S \$currQ
+# Outputs: Q
+FDSE_1 1008 1 5 1
+0 151 0 446 0
+
# SLICEM/A6LUT
# Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32}
# Necessary since RAMD* and SRL* have both combinatorial (i.e.
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L238-L250
+(* abc_box_id=1001, lib_whitebox, abc9_flop *)
module FDRE (
(* abc_arrival=303 *)
output reg Q,
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_R_INVERTED = 1'b0;
initial Q <= INIT;
+ wire \$currQ ;
+ reg \$nextQ ;
+ always @* if (R == !IS_R_INVERTED) \$nextQ = 1'b0; else if (CE) \$nextQ = D ^ IS_D_INVERTED; else \$nextQ = \$currQ ;
+`ifdef _ABC
+ // `abc9' requires that complex flops be split into a combinatorial
+ // box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
+ // In order to achieve clock-enable behaviour, the current value
+ // of the sequential output is required which Yosys will
+ // connect to the special `\$currQ' wire.
+
+ // Special signal indicating clock domain
+ // (used to partition the module so that `abc9' only performs
+ // sequential synthesis (reachability analysis) correctly on
+ // one domain at a time)
+ wire [1:0] \$abc9_clock = {C, IS_C_INVERTED};
+ // Special signal indicating control domain
+ // (which, combined with this spell type, encodes to `abc9'
+ // which flops may be merged together)
+ wire [3:0] \$abc9_control = {CE, IS_D_INVERTED, R, IS_R_INVERTED};
+ always @* Q = \$nextQ ;
+`else
+ assign \$currQ = Q;
generate case (|IS_C_INVERTED)
- 1'b0: always @(posedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
- 1'b1: always @(negedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
+ 1'b0: always @(posedge C) Q <= \$nextQ ;
+ 1'b1: always @(negedge C) Q <= \$nextQ ;
endcase endgenerate
+`endif
endmodule
-module FDSE (
+(* abc_box_id=1002, lib_whitebox, abc9_flop *)
+module FDRE_1 (
(* abc_arrival=303 *)
output reg Q,
(* clkbuf_sink *)
- (* invertible_pin = "IS_C_INVERTED" *)
input C,
- input CE,
- (* invertible_pin = "IS_D_INVERTED" *)
- input D,
- (* invertible_pin = "IS_S_INVERTED" *)
- input S
+ input CE, D, R
);
- parameter [0:0] INIT = 1'b1;
- parameter [0:0] IS_C_INVERTED = 1'b0;
- parameter [0:0] IS_D_INVERTED = 1'b0;
- parameter [0:0] IS_S_INVERTED = 1'b0;
+ parameter [0:0] INIT = 1'b0;
initial Q <= INIT;
- generate case (|IS_C_INVERTED)
- 1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
- 1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
- endcase endgenerate
+ wire \$currQ ;
+ reg \$nextQ ;
+ always @* if (R) Q <= 1'b0; else if (CE) Q <= D; else \$nextQ = \$currQ ;
+`ifdef _ABC
+ // `abc9' requires that complex flops be split into a combinatorial
+ // box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
+ // In order to achieve clock-enable behaviour, the current value
+ // of the sequential output is required which Yosys will
+ // connect to the special `\$currQ' wire.
+
+ // Special signal indicating clock domain
+ // (used to partition the module so that `abc9' only performs
+ // sequential synthesis (reachability analysis) correctly on
+ // one domain at a time)
+ wire [1:0] \$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
+ // Special signal indicating control domain
+ // (which, combined with this spell type, encodes to `abc9'
+ // which flops may be merged together)
+ wire [3:0] \$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */};
+ always @* Q = \$nextQ ;
+`else
+ assign \$currQ = Q;
+ always @(negedge C) Q <= \$nextQ ;
+`endif
endmodule
+(* abc_box_id=1003, lib_whitebox, abc9_flop *)
module FDCE (
(* abc_arrival=303 *)
output reg Q,
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_CLR_INVERTED = 1'b0;
initial Q <= INIT;
+ wire \$currQ ;
+ reg \$nextQ ;
+ always @* if (CE) Q <= D ^ IS_D_INVERTED; else \$nextQ = \$currQ ;
+`ifdef _ABC
+ // `abc9' requires that complex flops be split into a combinatorial
+ // box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
+ // In order to achieve clock-enable behaviour, the current value
+ // of the sequential output is required which Yosys will
+ // connect to the special `\$currQ' wire.
+ // Since this is an async flop, async behaviour is also dealt with
+ // using the $_ABC_ASYNC box by abc_map.v
+
+ // Special signal indicating clock domain
+ // (used to partition the module so that `abc9' only performs
+ // sequential synthesis (reachability analysis) correctly on
+ // one domain at a time)
+ wire [1:0] \$abc9_clock = {C, IS_C_INVERTED};
+ // Special signal indicating control domain
+ // (which, combined with this spell type, encodes to `abc9'
+ // which flops may be merged together)
+ wire [3:0] \$abc9_control = {CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED};
+ always @* Q = \$nextQ ;
+`else
+ assign \$currQ = Q;
generate case ({|IS_C_INVERTED, |IS_CLR_INVERTED})
- 2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
- 2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
- 2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
- 2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
+ 2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else Q <= \$nextQ ;
+ 2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else Q <= \$nextQ ;
+ 2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else Q <= \$nextQ ;
+ 2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else Q <= \$nextQ ;
endcase endgenerate
+`endif
endmodule
+(* abc_box_id=1004, lib_whitebox, abc9_flop *)
+module FDCE_1 (
+ (* abc_arrival=303 *)
+ output reg Q,
+ (* clkbuf_sink *)
+ input C,
+ input CE, D, CLR
+);
+ parameter [0:0] INIT = 1'b0;
+ initial Q <= INIT;
+ wire \$currQ ;
+ reg \$nextQ ;
+ always @* if (CE) Q <= D; else \$nextQ = \$currQ ;
+`ifdef _ABC
+ // `abc9' requires that complex flops be split into a combinatorial
+ // box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
+ // In order to achieve clock-enable behaviour, the current value
+ // of the sequential output is required which Yosys will
+ // connect to the special `\$currQ' wire.
+ // Since this is an async flop, async behaviour is also dealt with
+ // using the $_ABC_ASYNC box by abc_map.v
+
+ // Special signal indicating clock domain
+ // (used to partition the module so that `abc9' only performs
+ // sequential synthesis (reachability analysis) correctly on
+ // one domain at a time)
+ wire [1:0] \$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
+ // Special signal indicating control domain
+ // (which, combined with this spell type, encodes to `abc9'
+ // which flops may be merged together)
+ wire [3:0] \$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */};
+ always @* Q = \$nextQ ;
+`else
+ assign \$currQ = Q;
+ always @(negedge C, posedge CLR) if (CLR == !IS_CLR_INVERTED) Q <= 1'b0; else Q <= \$nextQ ;
+`endif
+endmodule
+
+(* abc_box_id=1005, lib_whitebox, abc9_flop *)
module FDPE (
(* abc_arrival=303 *)
output reg Q,
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_PRE_INVERTED = 1'b0;
initial Q <= INIT;
+ wire \$currQ ;
+ reg \$nextQ ;
+ always @* if (CE) Q <= D ^ IS_D_INVERTED; else \$nextQ = \$currQ ;
+`ifdef _ABC
+ // `abc9' requires that complex flops be split into a combinatorial
+ // box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
+ // In order to achieve clock-enable behaviour, the current value
+ // of the sequential output is required which Yosys will
+ // connect to the special `\$currQ' wire.
+ // Since this is an async flop, async behaviour is also dealt with
+ // using the $_ABC_ASYNC box by abc_map.v
+
+ // Special signal indicating clock domain
+ // (used to partition the module so that `abc9' only performs
+ // sequential synthesis (reachability analysis) correctly on
+ // one domain at a time)
+ wire [1:0] \$abc9_clock = {C, IS_C_INVERTED};
+ // Special signal indicating control domain
+ // (which, combined with this spell type, encodes to `abc9'
+ // which flops may be merged together)
+ wire [3:0] \$abc9_control = {CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED};
+ always @* Q = \$nextQ ;
+`else
+ assign \$currQ = Q;
generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED})
- 2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
- 2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
- 2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
- 2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
+ 2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= \$nextQ ;
+ 2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= \$nextQ ;
+ 2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= \$nextQ ;
+ 2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= \$nextQ ;
endcase endgenerate
+`endif
endmodule
-module FDRE_1 (
- (* abc_arrival=303 *)
- output reg Q,
- (* clkbuf_sink *)
- input C,
- input CE, D, R
-);
- parameter [0:0] INIT = 1'b0;
- initial Q <= INIT;
- always @(negedge C) if (R) Q <= 1'b0; else if(CE) Q <= D;
-endmodule
-
-module FDSE_1 (
+(* abc_box_id=1006, lib_whitebox, abc9_flop *)
+module FDPE_1 (
(* abc_arrival=303 *)
output reg Q,
(* clkbuf_sink *)
input C,
- input CE, D, S
+ input CE, D, PRE
);
parameter [0:0] INIT = 1'b1;
initial Q <= INIT;
- always @(negedge C) if (S) Q <= 1'b1; else if(CE) Q <= D;
+ wire \$currQ ;
+ reg \$nextQ ;
+ always @* if (CE) Q <= D; else \$nextQ = \$currQ ;
+`ifdef _ABC
+ // `abc9' requires that complex flops be split into a combinatorial
+ // box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
+ // In order to achieve clock-enable behaviour, the current value
+ // of the sequential output is required which Yosys will
+ // connect to the special `\$currQ' wire.
+ // Since this is an async flop, async behaviour is also dealt with
+ // using the $_ABC_ASYNC box by abc_map.v
+
+ // Special signal indicating clock domain
+ // (used to partition the module so that `abc9' only performs
+ // sequential synthesis (reachability analysis) correctly on
+ // one domain at a time)
+ wire [1:0] \$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
+ // Special signal indicating control domain
+ // (which, combined with this spell type, encodes to `abc9'
+ // which flops may be merged together)
+ wire [3:0] \$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */};
+ always @* Q = \$nextQ ;
+`else
+ assign \$currQ = Q;
+ always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else Q <= \$nextQ ;
+`endif
endmodule
-module FDCE_1 (
+(* abc_box_id=1007, lib_whitebox, abc9_flop *)
+module FDSE (
(* abc_arrival=303 *)
output reg Q,
(* clkbuf_sink *)
+ (* invertible_pin = "IS_C_INVERTED" *)
input C,
- input CE, D, CLR
+ input CE,
+ (* invertible_pin = "IS_D_INVERTED" *)
+ input D,
+ (* invertible_pin = "IS_S_INVERTED" *)
+ input S
);
- parameter [0:0] INIT = 1'b0;
+ parameter [0:0] INIT = 1'b1;
+ parameter [0:0] IS_C_INVERTED = 1'b0;
+ parameter [0:0] IS_D_INVERTED = 1'b0;
+ parameter [0:0] IS_S_INVERTED = 1'b0;
initial Q <= INIT;
- always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
+ wire \$currQ ;
+ reg \$nextQ ;
+ always @* if (S == !IS_S_INVERTED) \$nextQ = 1'b1; else if (CE) \$nextQ = D ^ IS_D_INVERTED; else \$nextQ = \$currQ ;
+`ifdef _ABC
+ // `abc9' requires that complex flops be split into a combinatorial
+ // box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
+ // In order to achieve clock-enable behaviour, the current value
+ // of the sequential output is required which Yosys will
+ // connect to the special `\$currQ' wire.
+
+ // Special signal indicating clock domain
+ // (used to partition the module so that `abc9' only performs
+ // sequential synthesis (reachability analysis) correctly on
+ // one domain at a time)
+ wire [1:0] \$abc9_clock = {C, IS_C_INVERTED};
+ // Special signal indicating control domain
+ // (which, combined with this spell type, encodes to `abc9'
+ // which flops may be merged together)
+ wire [3:0] \$abc9_control = {CE, IS_D_INVERTED, S, IS_S_INVERTED};
+ always @* Q = \$nextQ ;
+`else
+ assign \$currQ = Q;
+ generate case (|IS_C_INVERTED)
+ 1'b0: always @(posedge C) Q <= \$nextQ ;
+ 1'b1: always @(negedge C) Q <= \$nextQ ;
+ endcase endgenerate
+`endif
endmodule
-module FDPE_1 (
+(* abc_box_id=1008, lib_whitebox, abc9_flop *)
+module FDSE_1 (
(* abc_arrival=303 *)
output reg Q,
(* clkbuf_sink *)
input C,
- input CE, D, PRE
+ input CE, D, S
);
parameter [0:0] INIT = 1'b1;
initial Q <= INIT;
- always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
+ wire \$currQ ;
+ reg \$nextQ ;
+ always @* if (S) \$nextQ = 1'b1; else if (CE) \$nextQ = D; else \$nextQ = \$currQ ;
+`ifdef _ABC
+ // `abc9' requires that complex flops be split into a combinatorial
+ // box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
+ // In order to achieve clock-enable behaviour, the current value
+ // of the sequential output is required which Yosys will
+ // connect to the special `\$currQ' wire.
+
+ // Special signal indicating clock domain
+ // (used to partition the module so that `abc9' only performs
+ // sequential synthesis (reachability analysis) correctly on
+ // one domain at a time)
+ wire [1:0] \$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
+ // Special signal indicating control domain
+ // (which, combined with this spell type, encodes to `abc9'
+ // which flops may be merged together)
+ wire [3:0] \$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */};
+ always @* Q = \$nextQ ;
+`else
+ assign \$currQ = Q;
+ always @(negedge C) Q <= \$nextQ ;
+`endif
endmodule
module RAM32X1D (
if (check_label("begin")) {
if (vpr)
- run("read_verilog -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
+ run("read_verilog -lib -D_ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
else
- run("read_verilog -lib +/xilinx/cells_sim.v");
+ run("read_verilog -lib -D_ABC +/xilinx/cells_sim.v");
if (help_mode)
run("read_verilog -lib +/xilinx/{family}_cells_xtra.v");
projects / yosys.git / commitdiff