Copyright 2014-2015 / Florent Kermarrec / florent@enjoy-digital.fr
- A generic and configurable SATA1/2/3 core
+ A small footprint and configurable SATA core
developed in partnership with M-Labs Ltd & HKU
+[> Intro
+-----------
+LiteSATA provides a small footprint and configurable SATA core supporting SATA
+revisions 1, 2 and 3.
+
+LiteSATA is part of LiteX libraries whose aims is to lower entry level of complex
+FPGA IP cores by providing simple, elegant and efficient implementations of
+components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
+
+The core uses simple and specific streaming buses and will provides in the future
+adapters to use standardized AXI or Avalon-ST streaming buses.
+
+Since Python is used to describe the HDL, the core is highly and easily
+configurable.
+
+The synthetizable BIST can be used as a starting point to integrate SATA in
+your own SoC.
+
+LiteSATA uses technologies developed in partnership with M-Labs Ltd:
+ - Migen enables generating HDL with Python in an efficient way.
+ - MiSoC provides the basic blocks to build a powerful and small footprint SoC.
+
+LiteSATA can be used as a Migen/MiSoC library (by simply installing it
+with the provided setup.py) or can be integrated with your standard design flow
+by generating the verilog rtl that you will use as a standard core.
+
[> Features
------------------
PHY:
- - OOB, COMWAKE, COMINIT.
- - ALIGN inserter/remover and bytes alignment on K28.5.
- - 8B/10B encoding/decoding in transceiver.
- - Errors detection and reporting.
- - 1.5 / 3.0 / 6.0GBPs supported speeds.
- - 37.5 / 75 / 150MHz system clock.
+ - OOB, COMWAKE, COMINIT
+ - ALIGN inserter/remover and bytes alignment on K28.5
+ - 8B/10B encoding/decoding in transceiver
+ - Errors detection and reporting
+ - 32 bits interface
+ - 1.5/3.0/6.0GBps supported speeds (respectively 37.5/75/150MHz system clk)
Core:
Link:
- - CONT inserter/remover.
- - Scrambling/Descrambling of data.
- - CRC inserter/checker.
- - HOLD insertion/detection.
- - Errors detection and reporting.
+ - CONT inserter/remover
+ - Scrambling/Descrambling of data
+ - CRC inserter/checker
+ - HOLD insertion/detection
+ - Errors detection and reporting
Transport/Command:
- - Easy to use user interface (Can be used with or without CPU).
- - 48 bits sector addressing.
- - 3 supported commands: READ_DMA(_EXT), WRITE_DMA(_EXT), IDENTIFY_DEVICE.
- - Errors detection and reporting.
+ - Easy to use user interfaces (Can be used with or without CPU)
+ - 48 bits sector addressing
+ - 3 supported commands: READ_DMA(_EXT), WRITE_DMA(_EXT), IDENTIFY_DEVICE
+ - Errors detection and reporting
Frontend:
- Configurable crossbar (simply use core.crossbar.get_port() to add a new port!)
- - Ports arbitration transparent to the user.
- - Synthetizable BIST.
+ - Ports arbitration transparent to the user
+ - Synthetizable BIST
+
+[> Possibles improvements
+----------------------
+- add standardized adapters (AXI, Avalon-ST)
+- add NCQ support
+- add AES hardware encryption
+- add on-the-flow compression/decompression
+- add support for Altera PHYs.
+- add support for Lattice PHYs.
+- add support for Xilinx 7-Series GTP/GTH (currently only 7-Series GTX are
+ supported)
+- add Zynq Linux drivers.
+- ...
+
+If you want to support these features, please contact us at florent [AT]
+enjoy-digital.fr. You can also contact our partner on the public mailing list
+devel [AT] lists.m-labs.hk.
[> Getting started
------------------
-1. Install Python3 and Xilinx's Vivado software.
+1. Install Python3 and Xilinx's Vivado software
2. Obtain Migen and install it:
git clone https://github.com/enjoy-digital/migen
5. Copy lite-sata in working directory and move to it.
6. Build and load design:
- make all
+ python3 make.py all
7. Test design:
go to test directory and run:
python3 bist.py
-[> Simulations :
+[> Simulations:
Simulations are avalaible in ./lib/sata/test:
- crc_tb
- scrambler_tb
- link_tb
- command_tb
- bist_tb
- hdd.py is a HDD model implementing all SATA layers.
+ hdd.py is a simplified HDD model implementing all SATA layers.
To run a simulation, move to ./lib/sata/test and run:
make simulation_name
visualize the internal logic of the design and even inject the captured data in
the HDD model!
+[> License
+----------------------
+LiteSATA is released under the very permissive two-clause BSD license. Under the
+terms of this license, you are authorized to use Migen for closed-source
+proprietary designs.
+Even though we do not require you to do so, those things are awesome, so please
+do them if possible:
+ - tell us that you are using LiteSATA
+ - cite Migen in publications related to research it has helped
+ - send us feedback and suggestions for improvements
+ - send us bug reports when something goes wrong
+ - send us the modifications and improvements you have done to LiteSATA.
+
+[> Support
+----------------------
+We love open-source hardware and like sharing our designs with others. We think
+that providing this core with a BSD license will enable its easy reuse and
+customization without the usual restrictions of commercial cores.
+
+We also offer design services and can:
+- provide you commercial support for our cores.
+- customize our cores to fit your needs and help you to integrate it in your design.
+- create custom designs for you and provide our already proven cores for free.
+- ...
+
+So feel free to contact us, we'd love to work with you!
+
[> Contact
-E-mail: florent@enjoy-digital.fr
+E-mail: florent [AT] enjoy-digital.fr
--- /dev/null
+#!/usr/bin/env python3
+
+import sys, os, argparse, subprocess, struct, importlib
+
+from mibuild.tools import write_to_file
+from migen.util.misc import autotype
+from migen.fhdl import simplify
+
+from misoclib.gensoc import cpuif
+
+def _import(default, name):
+ return importlib.import_module(default + "." + name)
+
+def _get_args():
+ parser = argparse.ArgumentParser(formatter_class=argparse.RawDescriptionHelpFormatter,
+ description="""\
+LiteSATA verilog rtl generator - based on Migen.
+
+This program builds and/or loads LiteSATA components.
+One or several actions can be specified:
+
+clean delete previous build(s).
+build-rtl build verilog rtl.
+build-bitstream build-bitstream build FPGA bitstream.
+build-csr-csv save CSR map into CSV file.
+
+load-bitstream load bitstream into volatile storage.
+
+all clean, build-csr-csv, build-bitstream, load-bitstream.
+""")
+
+ parser.add_argument("-t", "--target", default="bist_kc705", help="Core type to build")
+ parser.add_argument("-s", "--sub-target", default="", help="variant of the Core type to build")
+ parser.add_argument("-p", "--platform", default=None, help="platform to build for")
+ parser.add_argument("-Ot", "--target-option", default=[], nargs=2, action="append", help="set target-specific option")
+ parser.add_argument("-Op", "--platform-option", default=[("programmer", "vivado")], nargs=2, action="append", help="set platform-specific option")
+ parser.add_argument("--csr_csv", default="./test/csr.csv", help="CSV file to save the CSR map into")
+
+ parser.add_argument("action", nargs="+", help="specify an action")
+
+ return parser.parse_args()
+
+# Note: misoclib need to be installed as a python library
+
+if __name__ == "__main__":
+ args = _get_args()
+
+ # create top-level Core object
+ target_module = _import("targets", args.target)
+ if args.sub_target:
+ top_class = getattr(target_module, args.sub_target)
+ else:
+ top_class = target_module.default_subtarget
+
+ if args.platform is None:
+ platform_name = top_class.default_platform
+ else:
+ platform_name = args.platform
+ platform_module = _import("platforms", platform_name)
+ platform_kwargs = dict((k, autotype(v)) for k, v in args.platform_option)
+ platform = platform_module.Platform(**platform_kwargs)
+
+ build_name = top_class.__name__.lower() + "-" + platform_name
+ top_kwargs = dict((k, autotype(v)) for k, v in args.target_option)
+ soc = top_class(platform, **top_kwargs)
+ soc.finalize()
+
+ # decode actions
+ action_list = ["clean", "build-csr-csv", "build-rtl", "build-bitstream", "load-bitstream", "all"]
+ actions = {k: False for k in action_list}
+ for action in args.action:
+ if action in actions:
+ actions[action] = True
+ else:
+ print("Unknown action: "+action+". Valid actions are:")
+ for a in action_list:
+ print(" "+a)
+ sys.exit(1)
+
+ print("""\
+# __ _ __ _______ _________
+# / / (_) /____ / __/ _ /_ __/ _ |
+# / /__/ / __/ -_)\ \/ __ |/ / / __ |
+# /____/_/\__/\__/___/_/ |_/_/ /_/ |_|
+#
+# a generic and configurable SATA core
+# based on Migen/MiSoC
+#
+#====== Building options: ======
+# SATA revision: {}
+# Integrated BIST: {}
+# Integrated Logic Analyzer: {}
+# Crossbar ports: {}
+#===============================""".format(soc.sata_phy.speed, hasattr(soc.sata, "bist"), hasattr(soc, "mila"), len(soc.sata.crossbar.slaves)))
+
+ # dependencies
+ if actions["all"]:
+ actions["clean"] = True
+ actions["build-csr-csv"] = True
+ actions["build-bitstream"] = True
+ actions["load-bitstream"] = True
+
+ if actions["build-rtl"]:
+ actions["clean"] = True
+ actions["build-csr-csv"] = True
+
+ if actions["build-bitstream"]:
+ actions["clean"] = True
+ actions["build-csr-csv"] = True
+ actions["build-bitstream"] = True
+ actions["load-bitstream"] = True
+
+ if actions["clean"]:
+ subprocess.call(["rm", "-rf", "build/*"])
+
+ if actions["build-csr-csv"]:
+ csr_csv = cpuif.get_csr_csv(soc.cpu_csr_regions)
+ write_to_file(args.csr_csv, csr_csv)
+
+ if actions["build-rtl"]:
+ raise NotImplementedError()
+
+ if actions["build-bitstream"]:
+ platform.build(soc, build_name=build_name)
+
+ if actions["load-bitstream"]:
+ prog = platform.create_programmer()
+ prog.load_bitstream("build/" + build_name + platform.bitstream_ext)
self.sata_core_command_tx_fsm_state.eq(self.sata.core.command.tx.fsm.state)
]
-#default_subtarget = BISTSoC
-default_subtarget = BISTSoCDevel
+default_subtarget = BISTSoC
projects / litex.git / commitdiff