Workaround for zero-delay loop simulation problem with Icarus Verilog. TODO: clarify...

diff --git a/milkymist/asmicon/multiplexer.py b/milkymist/asmicon/multiplexer.py
index 6ca619bb6e9dcde66bc16c53428e909d81054be8..ac4b2265c9070751984fcd013cc6560c83f23b7d 100644 (file)
--- a/milkymist/asmicon/multiplexer.py
+++ b/milkymist/asmicon/multiplexer.py
@@ -251,9 +251,10 @@ class Multiplexer:
                )
                fsm.act(fsm.REFRESH,
                        steerer.sel[0].eq(STEER_REFRESH),
-                       self.refresher.ack.eq(1),
                        If(~self.refresher.req, fsm.next_state(fsm.READ))
                )
+               # FIXME: workaround for zero-delay loop simulation problem with Icarus Verilog
+               comb.append(self.refresher.ack.eq(fsm._state == fsm.REFRESH))
                
                return Fragment(comb, sync) + \
                        choose_cmd.get_fragment() + \