command_tb: add random (still something to fix on TX)

diff --git a/lib/sata/test/command_tb.py b/lib/sata/test/command_tb.py
index fc1f441c7edac96247004e863bec0fc79646206b..59a786edc2f270c543b51936bc677f98a2861267 100644 (file)
--- a/lib/sata/test/command_tb.py
+++ b/lib/sata/test/command_tb.py
@@ -106,7 +106,7 @@ class TB(Module):
        def __init__(self):
                self.submodules.hdd = HDD(
                                phy_debug=False,
-                               link_random_level=0, link_debug=False,
+                               link_random_level=25, link_debug=False,
                                transport_debug=False, transport_loopback=False,
                                command_debug=False,
                                mem_debug=True)
@@ -115,17 +115,20 @@ class TB(Module):
                self.submodules.command = SATACommand(self.transport)
 
                self.submodules.streamer = CommandStreamer()
+               streamer_ack_randomizer = AckRandomizer(command_tx_description(32), level=0)
+               self.submodules += streamer_ack_randomizer
                self.submodules.logger = CommandLogger()
+               logger_ack_randomizer = AckRandomizer(command_rx_description(32), level=25)
+               self.submodules += logger_ack_randomizer
                self.comb += [
-                       Record.connect(self.streamer.source, self.command.sink),
-                       Record.connect(self.command.source, self.logger.sink)
+                       Record.connect(self.streamer.source, streamer_ack_randomizer.sink),
+                       Record.connect(streamer_ack_randomizer.source, self.command.sink),
+                       Record.connect(self.command.source, logger_ack_randomizer.sink),
+                       Record.connect(logger_ack_randomizer.source, self.logger.sink)
                ]
 
        def gen_simulation(self, selfp):
                self.hdd.allocate_mem(0x00000000, 64*1024*1024)
-               selfp.command.source.ack = 1
-               for i in range(100):
-                       yield
                write_data = [i for i in range(128)]
                write_packet = CommandTXPacket(write=1, address=1024, length=len(write_data), data=write_data)
                yield from self.streamer.send(write_packet)
@@ -141,4 +144,4 @@ class TB(Module):
                print("shift "+ str(s) + " / length " + str(l) + " / errors " + str(e))
 
 if __name__ == "__main__":
-       run_simulation(TB(), ncycles=512, vcd_name="my.vcd", keep_files=True)
+       run_simulation(TB(), ncycles=1024, vcd_name="my.vcd", keep_files=True)

diff --git a/lib/sata/transport/__init__.py b/lib/sata/transport/__init__.py
index 62e2d4a38e9f7ac1419851f456c39bade00ddddd..224171d54971e4ef55f25091ee04fc4855843b1d 100644 (file)
--- a/lib/sata/transport/__init__.py
+++ b/lib/sata/transport/__init__.py
@@ -60,7 +60,7 @@ class SATATransportTX(Module):
                fsm.act("SEND_REG_H2D_CMD",
                        _encode_cmd(sink, fis_reg_h2d_layout, encoded_cmd),
                        cmd_len.eq(fis_reg_h2d_cmd_len-1),
-                       cmd_send.eq(1),
+                       cmd_send.eq(sink.stb),
                        If(cmd_done,
                                sink.ack.eq(1),
                                NextState("IDLE")
@@ -70,7 +70,7 @@ class SATATransportTX(Module):
                        _encode_cmd(sink, fis_data_layout, encoded_cmd),
                        cmd_len.eq(fis_data_cmd_len-1),
                        cmd_with_data.eq(1),
-                       cmd_send.eq(1),
+                       cmd_send.eq(sink.stb),
                        If(cmd_done,
                                NextState("SEND_DATA")
                        )