genxml: Add L3 Cache Control register definitions

Based on intel_reg.h (5912da45a69923afa1b7f2eb5bb371d848813c41)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>

diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml
index 268ca3d97d7f68418ae3cf4ebc61a0e889ec1cc4..960df5eaf9f6b4fd66b1fcfe9242156430cab4e4 100644 (file)
--- a/src/intel/genxml/gen7.xml
+++ b/src/intel/genxml/gen7.xml
@@ -2508,4 +2508,31 @@
     <field name="SW Tessellation Memory Object Control State" start="40" end="43" type="MEMORY_OBJECT_CONTROL_STATE"/>
   </instruction>
 
+  <register name="L3SQCREG1" length="1" num="0xb010">
+    <field name="Convert DC_UC" start="24" end="24" type="uint"/>
+    <field name="Convert IS_UC" start="25" end="25" type="uint"/>
+    <field name="Convert C_UC" start="26" end="26" type="uint"/>
+    <field name="Convert T_UC" start="27" end="27" type="uint"/>
+  </register>
+
+  <register name="L3CNTLREG2" length="1" num="0xb020">
+    <field name="SLM Enable" start="0" end="0" type="uint"/>
+    <field name="URB Allocation" start="1" end="6" type="uint"/>
+    <field name="URB Low Bandwidth" start="7" end="7" type="uint"/>
+    <field name="ALL Allocation" start="8" end="13" type="uint"/>
+    <field name="RO Allocation" start="14" end="19" type="uint"/>
+    <field name="RO Low Bandwidth" start="20" end="20" type="uint"/>
+    <field name="DC Allocation" start="21" end="26" type="uint"/>
+    <field name="DC Low Bandwidth" start="27" end="27" type="uint"/>
+  </register>
+
+  <register name="L3CNTLREG3" length="1" num="0xb024">
+    <field name="IS Allocation" start="1" end="6" type="uint"/>
+    <field name="IS Low Bandwidth" start="7" end="7" type="uint"/>
+    <field name="C Allocation" start="8" end="13" type="uint"/>
+    <field name="C Low Bandwidth" start="14" end="14" type="uint"/>
+    <field name="T Allocation" start="15" end="20" type="uint"/>
+    <field name="T Low Bandwidth" start="21" end="21" type="uint"/>
+  </register>
+
 </genxml>

diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml
index 94bb64e595e971c1d30475c1d55d0b8193fbe935..26c1f9ecdf622fd23d8f4d009adc525c033985fd 100644 (file)
--- a/src/intel/genxml/gen75.xml
+++ b/src/intel/genxml/gen75.xml
@@ -2906,4 +2906,30 @@
     <field name="SW Tessellation Memory Object Control State" start="40" end="43" type="MEMORY_OBJECT_CONTROL_STATE"/>
   </instruction>
 
+  <register name="L3SQCREG1" length="1" num="0xb010">
+    <field name="Convert DC_UC" start="24" end="24" type="uint"/>
+    <field name="Convert IS_UC" start="25" end="25" type="uint"/>
+    <field name="Convert C_UC" start="26" end="26" type="uint"/>
+    <field name="Convert T_UC" start="27" end="27" type="uint"/>
+  </register>
+
+  <register name="L3CNTLREG2" length="1" num="0xb020">
+    <field name="SLM Enable" start="0" end="0" type="uint"/>
+    <field name="URB Allocation" start="1" end="6" type="uint"/>
+    <field name="URB Low Bandwidth" start="7" end="7" type="uint"/>
+    <field name="RO Allocation" start="14" end="19" type="uint"/>
+    <field name="RO Low Bandwidth" start="20" end="20" type="uint"/>
+    <field name="DC Allocation" start="21" end="26" type="uint"/>
+    <field name="DC Low Bandwidth" start="27" end="27" type="uint"/>
+  </register>
+
+  <register name="L3CNTLREG3" length="1" num="0xb024">
+    <field name="IS Allocation" start="1" end="6" type="uint"/>
+    <field name="IS Low Bandwidth" start="7" end="7" type="uint"/>
+    <field name="C Allocation" start="8" end="13" type="uint"/>
+    <field name="C Low Bandwidth" start="14" end="14" type="uint"/>
+    <field name="T Allocation" start="15" end="20" type="uint"/>
+    <field name="T Low Bandwidth" start="21" end="21" type="uint"/>
+  </register>
+
 </genxml>

diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
index 96eda7034536ce8f2b8e21e1a35861e266f0f93f..694e691e5eab20e1a3cb861cf569979159d061a3 100644 (file)
--- a/src/intel/genxml/gen8.xml
+++ b/src/intel/genxml/gen8.xml
@@ -3163,4 +3163,12 @@
     <field name="SW Tessellation Memory Object Control State" start="40" end="43" type="MEMORY_OBJECT_CONTROL_STATE"/>
   </instruction>
 
+  <register name="L3CNTLREG" length="1" num="0x7034">
+    <field name="SLM Enable" start="0" end="0" type="uint"/>
+    <field name="URB Allocation" start="1" end="7" type="uint"/>
+    <field name="RO Allocation" start="11" end="17" type="uint"/>
+    <field name="DC Allocation" start="18" end="24" type="uint"/>
+    <field name="All Allocation" start="25" end="31" type="uint"/>
+  </register>
+
 </genxml>

diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
index 79d3006d24b64d1df332506a3c7de9b099a249a0..bc2639a7878e74dfd85da9d7cd02cd060a7a0e1b 100644 (file)
--- a/src/intel/genxml/gen9.xml
+++ b/src/intel/genxml/gen9.xml
@@ -3467,4 +3467,12 @@
     <field name="System Instruction Pointer" start="36" end="95" type="offset"/>
   </instruction>
 
+  <register name="L3CNTLREG" length="1" num="0x7034">
+    <field name="SLM Enable" start="0" end="0" type="uint"/>
+    <field name="URB Allocation" start="1" end="7" type="uint"/>
+    <field name="RO Allocation" start="11" end="17" type="uint"/>
+    <field name="DC Allocation" start="18" end="24" type="uint"/>
+    <field name="All Allocation" start="25" end="31" type="uint"/>
+  </register>
+
 </genxml>