radeonsi: enable ARB_query_buffer_object (v2)
authorNicolai Hähnle <nicolai.haehnle@amd.com>
Wed, 14 Sep 2016 07:43:42 +0000 (09:43 +0200)
committerNicolai Hähnle <nicolai.haehnle@amd.com>
Thu, 29 Sep 2016 09:15:00 +0000 (11:15 +0200)
v2: enable only when compute is available

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
docs/features.txt
docs/relnotes/12.1.0.html
src/gallium/drivers/radeonsi/si_pipe.c

index fbb3952b3c7aceaabd601a990c185f0a91dae9bc..037ee97f240f467963ba760fe725e5f2a3f7c548 100644 (file)
@@ -201,7 +201,7 @@ GL 4.4, GLSL 4.40 -- all DONE: i965/gen8+
   - specified transform/feedback layout                 DONE
   - input/output block locations                        DONE
   GL_ARB_multi_bind                                     DONE (all drivers)
-  GL_ARB_query_buffer_object                            DONE (i965/hsw+, nvc0)
+  GL_ARB_query_buffer_object                            DONE (i965/hsw+, nvc0, radeonsi)
   GL_ARB_texture_mirror_clamp_to_edge                   DONE (i965, nv50, nvc0, r600, radeonsi, llvmpipe, softpipe, swr)
   GL_ARB_texture_stencil8                               DONE (i965/hsw+, nv50, nvc0, r600, radeonsi, llvmpipe, softpipe, swr)
   GL_ARB_vertex_type_10f_11f_11f_rev                    DONE (i965, nv50, nvc0, r600, radeonsi, llvmpipe, softpipe, swr)
index cdd89092f539f7aab5445d63d338f814e9b202d2..dd179794b446d29ac58e5a42d611b6937ec97496 100644 (file)
@@ -52,6 +52,7 @@ Note: some of the new features are only available with certain drivers.
 <li>GL_ARB_cull_distance on radeonsi</li>
 <li>GL_ARB_enhanced_layouts on i965</li>
 <li>GL_ARB_indirect_parameters on radeonsi</li>
+<li>GL_ARB_query_buffer_object on radeonsi</li>
 <li>GL_ARB_shader_draw_parameters on radeonsi</li>
 <li>GL_ARB_shader_group_vote on nvc0</li>
 <li>GL_ARB_shader_viewport_layer_array on i965/gen6+</li>
index 730be9d55da2a4fcf967b7cce452f13b45fdd1a8..60ef5485855426cdbe79bff6064baf812a7960e1 100644 (file)
@@ -316,6 +316,16 @@ fail:
 /*
  * pipe_screen
  */
+static bool si_have_tgsi_compute(struct si_screen *sscreen)
+{
+       /* Old kernels disallowed some register writes for SI
+        * that are used for indirect dispatches. */
+       return HAVE_LLVM >= 0x309 &&
+              (sscreen->b.chip_class >= CIK ||
+               sscreen->b.info.drm_major == 3 ||
+               (sscreen->b.info.drm_major == 2 &&
+                sscreen->b.info.drm_minor >= 45));
+}
 
 static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 {
@@ -448,12 +458,14 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
        case PIPE_CAP_FAKE_SW_MSAA:
        case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
        case PIPE_CAP_VERTEXID_NOBASE:
-       case PIPE_CAP_QUERY_BUFFER_OBJECT:
        case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
        case PIPE_CAP_TGSI_VOTE:
        case PIPE_CAP_MAX_WINDOW_RECTANGLES:
                return 0;
 
+       case PIPE_CAP_QUERY_BUFFER_OBJECT:
+               return si_have_tgsi_compute(sscreen);
+
        case PIPE_CAP_DRAW_PARAMETERS:
        case PIPE_CAP_MULTI_DRAW_INDIRECT:
        case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
@@ -567,12 +579,7 @@ static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enu
                case PIPE_SHADER_CAP_SUPPORTED_IRS: {
                        int ir = 1 << PIPE_SHADER_IR_NATIVE;
 
-                       /* Old kernels disallowed some register writes for SI
-                        * that are used for indirect dispatches. */
-                       if (HAVE_LLVM >= 0x309 && (sscreen->b.chip_class >= CIK ||
-                                                  sscreen->b.info.drm_major == 3 ||
-                                                  (sscreen->b.info.drm_major == 2 &&
-                                                   sscreen->b.info.drm_minor >= 45)))
+                       if (si_have_tgsi_compute(sscreen))
                                ir |= 1 << PIPE_SHADER_IR_TGSI;
 
                        return ir;