- specified transform/feedback layout DONE
- input/output block locations DONE
GL_ARB_multi_bind DONE (all drivers)
- GL_ARB_query_buffer_object DONE (i965/hsw+, nvc0)
+ GL_ARB_query_buffer_object DONE (i965/hsw+, nvc0, radeonsi)
GL_ARB_texture_mirror_clamp_to_edge DONE (i965, nv50, nvc0, r600, radeonsi, llvmpipe, softpipe, swr)
GL_ARB_texture_stencil8 DONE (i965/hsw+, nv50, nvc0, r600, radeonsi, llvmpipe, softpipe, swr)
GL_ARB_vertex_type_10f_11f_11f_rev DONE (i965, nv50, nvc0, r600, radeonsi, llvmpipe, softpipe, swr)
<li>GL_ARB_cull_distance on radeonsi</li>
<li>GL_ARB_enhanced_layouts on i965</li>
<li>GL_ARB_indirect_parameters on radeonsi</li>
+<li>GL_ARB_query_buffer_object on radeonsi</li>
<li>GL_ARB_shader_draw_parameters on radeonsi</li>
<li>GL_ARB_shader_group_vote on nvc0</li>
<li>GL_ARB_shader_viewport_layer_array on i965/gen6+</li>
/*
* pipe_screen
*/
+static bool si_have_tgsi_compute(struct si_screen *sscreen)
+{
+ /* Old kernels disallowed some register writes for SI
+ * that are used for indirect dispatches. */
+ return HAVE_LLVM >= 0x309 &&
+ (sscreen->b.chip_class >= CIK ||
+ sscreen->b.info.drm_major == 3 ||
+ (sscreen->b.info.drm_major == 2 &&
+ sscreen->b.info.drm_minor >= 45));
+}
static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
{
case PIPE_CAP_FAKE_SW_MSAA:
case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
case PIPE_CAP_VERTEXID_NOBASE:
- case PIPE_CAP_QUERY_BUFFER_OBJECT:
case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
case PIPE_CAP_TGSI_VOTE:
case PIPE_CAP_MAX_WINDOW_RECTANGLES:
return 0;
+ case PIPE_CAP_QUERY_BUFFER_OBJECT:
+ return si_have_tgsi_compute(sscreen);
+
case PIPE_CAP_DRAW_PARAMETERS:
case PIPE_CAP_MULTI_DRAW_INDIRECT:
case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
case PIPE_SHADER_CAP_SUPPORTED_IRS: {
int ir = 1 << PIPE_SHADER_IR_NATIVE;
- /* Old kernels disallowed some register writes for SI
- * that are used for indirect dispatches. */
- if (HAVE_LLVM >= 0x309 && (sscreen->b.chip_class >= CIK ||
- sscreen->b.info.drm_major == 3 ||
- (sscreen->b.info.drm_major == 2 &&
- sscreen->b.info.drm_minor >= 45)))
+ if (si_have_tgsi_compute(sscreen))
ir |= 1 << PIPE_SHADER_IR_TGSI;
return ir;