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must read off of ibus in wb_get TestRunnerBase
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 15 Dec 2021 15:47:06 +0000 (15:47 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 15 Dec 2021 15:47:06 +0000 (15:47 +0000)
src/openpower/test/runner.py patch | blob | history

diff --git a/src/openpower/test/runner.py b/src/openpower/test/runner.py
index 91e3c79a23e8864179406b5a116322ff2afdb0f0..fd6540253b85c1cddd92af317487193ba59ec076 100644 (file)
--- a/src/openpower/test/runner.py
+++ b/src/openpower/test/runner.py
@@ -474,7 +474,7 @@ class TestRunnerBase(FHDLTestCase):
             default_mem = self.rom
             sim.add_sync_process(wrap(wb_get(dcache.bus,
                                              default_mem, "DCACHE")))
-            sim.add_sync_process(wrap(wb_get(icache.bus,
+            sim.add_sync_process(wrap(wb_get(icache.ibus,
                                              default_mem, "ICACHE")))
 
         with sim.write_vcd("issuer_simulator.vcd"):