[AArch64] Fix +sve documentation

The documentation entry for the SVE feature incorrectly said that
it was enabled by default for ARMv8-A or later.  This patch fixes
that and also mentions that +sve implies +simd.  (It also implies
+fp, but that follows by transitivity.)

gas/
	* doc/c-aarch64.texi: Fix sve entry.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 18440857637f3d241d8fae8524e6557bf3f54c82..1a2949c2c393b6a9c00cdf293530b1cf265eb288 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,7 @@
+2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * doc/c-aarch64.texi: Fix sve entry.
+
 2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
 
        * config/tc-arc.c (md_convert_frag): Remove @pcl relocation

diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 618f30026d41dd2ad95474d827eccee078c8b7cd..59467c55f9f410284fed347ff900a0fbb7b1b863 100644 (file)
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -155,8 +155,8 @@ automatically cause those extensions to be disabled.
  @tab Enable ARMv8.1 Advanced SIMD extensions.  This implies @code{simd}.
 @item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
  @tab Enable Advanced SIMD extensions.  This implies @code{fp}.
-@item @code{sve} @tab ARMv8-A @tab ARMv8-A or later
- @tab Enable the Scalable Vector Extensions.
+@item @code{sve} @tab ARMv8-A @tab No
+ @tab Enable the Scalable Vector Extensions.  This implies @code{simd}.
 @end multitable
 
 @node AArch64 Syntax