-PYTHON=
-
-all: build/soc.map
+PYTHON=c:\Python32\python
+all: build/de0_nano.sta
# We need to change to the build directory because the Quartus tools
# tend to dump a mess of various files in the current directory.
-build/soc.qsf:
+build/de0_nano.qsf:
$(PYTHON) build.py
-build/soc.map: build/soc.qsf
- cp soc.qpf build/de0_nano.qpf
+build/de0_nano.map: build/de0_nano.qsf
+ cp de0_nano.qpf build/de0_nano.qpf
cd build && quartus_map de0_nano.qpf
+
+build/de0_nano.fit: build/de0_nano.map
+ cd build && quartus_fit de0_nano.qpf
+
+build/de0_nano.asm: build/de0_nano.fit
+ cd build && quartus_asm de0_nano.qpf
+
+build/de0_nano.sta: build/de0_nano.asm
+ cd build && quartus_sta de0_nano.qpf
clean:
rm -rf build/*
class Constraints:
- def __init__(self):
+ def __init__(self, in_clk, in_rst, spi2csr0, led0):
self.constraints = []
def add(signal, pin, vec=-1, iostandard="3.3-V LVTTL", extra="", sch=""):
self.constraints.append((signal, vec, pin, iostandard, extra,sch))
for p in pins:
add(signal, p, i, iostandard, extra)
i += 1
-
+ # sys_clk
+ add(in_clk, "R8") # CLOCK_50
+
+ # sys_rst
+ add(in_rst, "J15") # KEY[0]
+
+ # spi2csr0
+ add(spi2csr0.spi_clk, "A14") #GPIO_2[0]
+ add(spi2csr0.spi_cs_n, "B16") #GPIO_2[1]
+ add(spi2csr0.spi_mosi, "C14") #GPIO_2[2]
+ add(spi2csr0.spi_miso, "C16") #GPIO_2[3]
+
+ # led0
+ add_vec(led0, ["A15", "A13", "B13", "A11",
+ "D1" , "F3" , "B1" , "L3"])
+
+
def get_ios(self):
return set([c[0] for c in self.constraints])
r += """
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE22F17C6
-set_global_assignment -name TOP_LEVEL_ENTITY "soc"
+set_global_assignment -name TOP_LEVEL_ENTITY "de0_nano"
set_global_assignment -name DEVICE_FILTER_PACKAGE FPGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 256
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6
--- /dev/null
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2009 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 9.0 Build 132 02/25/2009 SJ Full Version
+# Date created = 11:09:38 March 18, 2009
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "9.0"
+DATE = "11:09:38 March 18, 2009"
+
+# Revisions
+
+PROJECT_REVISION = "soc"
+++ /dev/null
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2009 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions
-# and other software and tools, and its AMPP partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Altera Program License
-# Subscription Agreement, Altera MegaCore Function License
-# Agreement, or other applicable license agreement, including,
-# without limitation, that your use is for the sole purpose of
-# programming logic devices manufactured by Altera and sold by
-# Altera or its authorized distributors. Please refer to the
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II
-# Version 9.0 Build 132 02/25/2009 SJ Full Version
-# Date created = 11:09:38 March 18, 2009
-#
-# -------------------------------------------------------------------------- #
-
-QUARTUS_VERSION = "9.0"
-DATE = "11:09:38 March 18, 2009"
-
-# Revisions
-
-PROJECT_REVISION = "soc"
sig_gen.eq(sig_gen+1)
]
+ # Led
+ led0 = Signal(BV(8))
+ comb += [
+ led0.eq(control_reg0.field.r[:8])
+ ]
+
+
# Dat / Trig Bus
comb += [
trigger0.in_trig.eq(sig_gen),
# HouseKeeping
+ in_clk = Signal()
+ in_rst = Signal()
frag = autofragment.from_local()
frag += Fragment(sync=sync,comb=comb)
- cst = Constraints()
+ cst = Constraints(in_clk, in_rst, spi2csr0, led0)
src_verilog, vns = verilog.convert(frag,
cst.get_ios(),
name="de0_nano",
+ clk_signal = in_clk,
+ rst_signal = in_rst,
return_ns=True)
src_qsf = cst.get_qsf(vns)
return (src_verilog, src_qsf)
\ No newline at end of file
projects / litex.git / commitdiff