// M5 special opcodes use the reserved 0x01 opcode space
0x01: decode M5FUNC {
0x00: arm({{
- AlphaPseudo::arm(xc->tcBase());
+ PseudoInst::arm(xc->tcBase());
}}, IsNonSpeculative);
0x01: quiesce({{
- AlphaPseudo::quiesce(xc->tcBase());
+ PseudoInst::quiesce(xc->tcBase());
}}, IsNonSpeculative, IsQuiesce);
0x02: quiesceNs({{
- AlphaPseudo::quiesceNs(xc->tcBase(), R16);
+ PseudoInst::quiesceNs(xc->tcBase(), R16);
}}, IsNonSpeculative, IsQuiesce);
0x03: quiesceCycles({{
- AlphaPseudo::quiesceCycles(xc->tcBase(), R16);
+ PseudoInst::quiesceCycles(xc->tcBase(), R16);
}}, IsNonSpeculative, IsQuiesce, IsUnverifiable);
0x04: quiesceTime({{
- R0 = AlphaPseudo::quiesceTime(xc->tcBase());
+ R0 = PseudoInst::quiesceTime(xc->tcBase());
}}, IsNonSpeculative, IsUnverifiable);
0x10: ivlb({{
warn_once("Obsolete M5 instruction ivlb encountered.\n");
warn_once("Obsolete M5 instruction ivlb encountered.\n");
}});
0x20: m5exit_old({{
- AlphaPseudo::m5exit_old(xc->tcBase());
+ PseudoInst::m5exit_old(xc->tcBase());
}}, No_OpClass, IsNonSpeculative);
0x21: m5exit({{
- AlphaPseudo::m5exit(xc->tcBase(), R16);
+ PseudoInst::m5exit(xc->tcBase(), R16);
}}, No_OpClass, IsNonSpeculative);
0x31: loadsymbol({{
- AlphaPseudo::loadsymbol(xc->tcBase());
+ PseudoInst::loadsymbol(xc->tcBase());
}}, No_OpClass, IsNonSpeculative);
0x30: initparam({{ Ra = xc->tcBase()->getCpuPtr()->system->init_param; }});
0x40: resetstats({{
- AlphaPseudo::resetstats(xc->tcBase(), R16, R17);
+ PseudoInst::resetstats(xc->tcBase(), R16, R17);
}}, IsNonSpeculative);
0x41: dumpstats({{
- AlphaPseudo::dumpstats(xc->tcBase(), R16, R17);
+ PseudoInst::dumpstats(xc->tcBase(), R16, R17);
}}, IsNonSpeculative);
0x42: dumpresetstats({{
- AlphaPseudo::dumpresetstats(xc->tcBase(), R16, R17);
+ PseudoInst::dumpresetstats(xc->tcBase(), R16, R17);
}}, IsNonSpeculative);
0x43: m5checkpoint({{
- AlphaPseudo::m5checkpoint(xc->tcBase(), R16, R17);
+ PseudoInst::m5checkpoint(xc->tcBase(), R16, R17);
}}, IsNonSpeculative);
0x50: m5readfile({{
- R0 = AlphaPseudo::readfile(xc->tcBase(), R16, R17, R18);
+ R0 = PseudoInst::readfile(xc->tcBase(), R16, R17, R18);
}}, IsNonSpeculative);
0x51: m5break({{
- AlphaPseudo::debugbreak(xc->tcBase());
+ PseudoInst::debugbreak(xc->tcBase());
}}, IsNonSpeculative);
0x52: m5switchcpu({{
- AlphaPseudo::switchcpu(xc->tcBase());
+ PseudoInst::switchcpu(xc->tcBase());
}}, IsNonSpeculative);
0x53: m5addsymbol({{
- AlphaPseudo::addsymbol(xc->tcBase(), R16, R17);
+ PseudoInst::addsymbol(xc->tcBase(), R16, R17);
}}, IsNonSpeculative);
0x54: m5panic({{
panic("M5 panic instruction called at pc=%#x.", xc->readPC());
}}, IsNonSpeculative);
0x55: m5anBegin({{
- AlphaPseudo::anBegin(xc->tcBase(), R16);
+ PseudoInst::anBegin(xc->tcBase(), R16);
}}, IsNonSpeculative);
0x56: m5anWait({{
- AlphaPseudo::anWait(xc->tcBase(), R16, R17);
+ PseudoInst::anWait(xc->tcBase(), R16, R17);
}}, IsNonSpeculative);
}
}
def bitfield I <13>;
def bitfield IMM_ASI <12:5>;
def bitfield IMM22 <21:0>;
+def bitfield M5FUNC <15:7>;
def bitfield MMASK <3:0>;
def bitfield OP <31:30>;
def bitfield OP2 <24:22>;
0x80: Trap::shutdown({{fault = new IllegalInstruction;}});
0x81: FailUnimpl::siam();
}
- 0x37: Trap::impdep2({{fault = new IllegalInstruction;}});
+ // M5 special opcodes use the reserved IMPDEP2A opcode space
+ 0x37: decode M5FUNC {
+ // we have 7 bits of space here to play with...
+ 0x21: m5exit({{PseudoInst::m5exit(xc->tcBase(), O0);
+ }}, No_OpClass, IsNonSpeculative);
+ 0x54: m5panic({{
+ panic("M5 panic instruction called at pc=%#x.", xc->readPC());
+ }}, No_OpClass, IsNonSpeculative);
+
+ }
0x38: Branch::jmpl({{
Addr target = Rs1 + Rs2_or_imm13;
if(target & 0x3)
}
}}, IsSerializeAfter, IsNonSpeculative);
}
- 0x3B: Nop::flush({{/*Instruction memory flush*/}});
+ 0x3B: Nop::flush({{/*Instruction memory flush*/}}, IsWriteBarrier,
+ MemWriteOp);
0x3C: save({{
if(Cansave == 0)
{
#include <ieeefp.h>
#endif
+#if FULL_SYSTEM
+#include "sim/pseudo_inst.hh"
+#endif
+
#include <limits>
#include <cmath>
'R1': ('IntReg', 'udw', '1', None, 7),
'R15': ('IntReg', 'udw', '15', 'IsInteger', 8),
'R16': ('IntReg', 'udw', '16', None, 9),
+ 'O0': ('IntReg', 'udw', '24', 'IsInteger', 10),
+ 'O1': ('IntReg', 'udw', '25', 'IsInteger', 11),
+ 'O2': ('IntReg', 'udw', '26', 'IsInteger', 12),
+ 'O3': ('IntReg', 'udw', '27', 'IsInteger', 13),
+ 'O4': ('IntReg', 'udw', '28', 'IsInteger', 14),
+ 'O5': ('IntReg', 'udw', '29', 'IsInteger', 15),
# Control registers
# 'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 40),
// Be fast if we can!
if (cacheValid && cacheState == tlbdata) {
- if (cacheEntry[0] && cacheAsi[0] == asi && cacheEntry[0]->range.va < vaddr + size &&
- cacheEntry[0]->range.va + cacheEntry[0]->range.size > vaddr &&
- (!write || cacheEntry[0]->pte.writable())) {
- req->setPaddr(cacheEntry[0]->pte.paddr() & ~(cacheEntry[0]->pte.size()-1) |
- vaddr & cacheEntry[0]->pte.size()-1 );
- return NoFault;
- }
- if (cacheEntry[1] && cacheAsi[1] == asi && cacheEntry[1]->range.va < vaddr + size &&
- cacheEntry[1]->range.va + cacheEntry[1]->range.size > vaddr &&
- (!write || cacheEntry[1]->pte.writable())) {
- req->setPaddr(cacheEntry[1]->pte.paddr() & ~(cacheEntry[1]->pte.size()-1) |
- vaddr & cacheEntry[1]->pte.size()-1 );
- return NoFault;
- }
- }
+
+
+
+ if (cacheEntry[0]) {
+ TlbEntry *ce = cacheEntry[0];
+ Addr ce_va = ce->range.va;
+ if (cacheAsi[0] == asi &&
+ ce_va < vaddr + size && ce_va + ce->range.size > vaddr &&
+ (!write || ce->pte.writable())) {
+ req->setPaddr(ce->pte.paddrMask() | vaddr & ce->pte.sizeMask());
+ if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1)
+ req->setFlags(req->getFlags() | UNCACHEABLE);
+ DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
+ return NoFault;
+ } // if matched
+ } // if cache entry valid
+ if (cacheEntry[1]) {
+ TlbEntry *ce = cacheEntry[1];
+ Addr ce_va = ce->range.va;
+ if (cacheAsi[1] == asi &&
+ ce_va < vaddr + size && ce_va + ce->range.size > vaddr &&
+ (!write || ce->pte.writable())) {
+ req->setPaddr(ce->pte.paddrMask() | vaddr & ce->pte.sizeMask());
+ if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1)
+ req->setFlags(req->getFlags() | UNCACHEABLE);
+ DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
+ return NoFault;
+ } // if matched
+ } // if cache entry valid
+ }
bool red = bits(tlbdata,1,1);
bool priv = bits(tlbdata,2,2);
}
- if (e->pte.sideffect())
+ if (e->pte.sideffect() || (e->pte.paddr() >> 39) & 1)
req->setFlags(req->getFlags() | UNCACHEABLE);
// cache translation date for next translation
using namespace Stats;
using namespace TheISA;
-namespace AlphaPseudo
+namespace PseudoInst
{
void
arm(ThreadContext *tc)
//We need the "Tick" and "Addr" data types from here
#include "sim/host.hh"
-namespace AlphaPseudo
+namespace PseudoInst
{
/**
* @todo these externs are only here for a hack in fullCPU::takeOver...
+++ /dev/null
-# Copyright (c) 2005-2006 The Regents of The University of Michigan
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Nathan Binkert
-# Ali Saidi
-
-### If we are not compiling on an alpha, we must use cross tools ###
-ifneq ($(shell uname -m), alpha)
-CROSS_COMPILE?=alpha-unknown-linux-gnu-
-endif
-CC=$(CROSS_COMPILE)gcc
-AS=$(CROSS_COMPILE)as
-LD=$(CROSS_COMPILE)ld
-
-CFLAGS=-O2
-OBJS=m5.o m5op.o
-
-all: m5
-
-%.o: %.S
- $(CC) $(CFLAGS) -o $@ -c $<
-
-%.o: %.c
- $(CC) $(CFLAGS) -o $@ -c $<
-
-m5: $(OBJS)
- $(CC) -o $@ $(OBJS)
-
-clean:
- rm -f *.o m5
--- /dev/null
+# Copyright (c) 2005-2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+# Ali Saidi
+
+### If we are not compiling on an alpha, we must use cross tools ###
+ifneq ($(shell uname -m), alpha)
+CROSS_COMPILE?=alpha-unknown-linux-gnu-
+endif
+CC=$(CROSS_COMPILE)gcc
+AS=$(CROSS_COMPILE)as
+LD=$(CROSS_COMPILE)ld
+
+CFLAGS=-O2
+OBJS=m5.o m5op_alpha.o
+
+all: m5
+
+%.o: %.S
+ $(CC) $(CFLAGS) -o $@ -c $<
+
+%.o: %.c
+ $(CC) $(CFLAGS) -o $@ -c $<
+
+m5: $(OBJS)
+ $(CC) -o $@ $(OBJS)
+
+clean:
+ rm -f *.o m5
--- /dev/null
+# Copyright (c) 2005-2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+# Ali Saidi
+
+### If we are not compiling on an alpha, we must use cross tools ###
+ifneq ($(shell uname -m), sun4v)
+CROSS_COMPILE?=sparc64-sun-solaris2.10-
+endif
+CC=$(CROSS_COMPILE)gcc
+AS=$(CROSS_COMPILE)as
+LD=$(CROSS_COMPILE)ld
+
+CFLAGS=-O2
+OBJS=m5.o m5op_sparc.o
+
+all: m5
+
+%.o: %.S
+ $(CC) $(CFLAGS) -o $@ -c $<
+
+%.o: %.c
+ $(CC) $(CFLAGS) -o $@ -c $<
+
+m5: $(OBJS)
+ $(CC) -o $@ $(OBJS)
+
+clean:
+ rm -f *.o m5
command = argv[1];
- if (COMPARE("ivlb")) {
- if (argc != 3)
- usage();
-
- arg1 = strtoul(argv[2], NULL, 0);
- m5_ivlb(arg1);
- return 0;
- }
-
- if (COMPARE("ivle")) {
- if (argc != 3)
- usage();
-
- arg1 = strtoul(argv[2], NULL, 0);
- m5_ivle(arg1);
- return 0;
- }
-
if (COMPARE("initparam")) {
if (argc != 2)
usage();
if (COMPARE("loadsymbol")) {
m5_loadsymbol(arg1);
return 0;
+ }
if (COMPARE("readfile")) {
char buf[256*1024];
int offset = 0;
+++ /dev/null
-/*
- * Copyright (c) 2003-2006 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Nathan Binkert
- * Ali Saidi
- */
-
-#define m5_op 0x01
-
-#define arm_func 0x00
-#define quiesce_func 0x01
-#define quiescens_func 0x02
-#define quiescecycle_func 0x03
-#define quiescetime_func 0x04
-#define ivlb 0x10 // obsolete
-#define ivle 0x11 // obsolete
-#define exit_old_func 0x20 // deprecated!
-#define exit_func 0x21
-#define initparam_func 0x30
-#define loadsymbol_func 0x31
-#define resetstats_func 0x40
-#define dumpstats_func 0x41
-#define dumprststats_func 0x42
-#define ckpt_func 0x43
-#define readfile_func 0x50
-#define debugbreak_func 0x51
-#define switchcpu_func 0x52
-#define addsymbol_func 0x53
-#define panic_func 0x54
-#define anbegin_func 0x55
-#define anwait_func 0x56
-
-#define INST(op, ra, rb, func) \
- .long (((op) << 26) | ((ra) << 21) | ((rb) << 16) | (func))
-
-#define LEAF(func) \
- .align 3; \
- .globl func; \
- .ent func; \
-func:
-
-#define RET \
- ret ($26)
-
-#define END(func) \
- .end func
-
-#define ARM(reg) INST(m5_op, reg, 0, arm_func)
-#define QUIESCE INST(m5_op, 0, 0, quiesce_func)
-#define QUIESCENS(r1) INST(m5_op, r1, 0, quiescens_func)
-#define QUIESCECYC(r1) INST(m5_op, r1, 0, quiescecycle_func)
-#define QUIESCETIME INST(m5_op, 0, 0, quiescetime_func)
-#define M5EXIT(reg) INST(m5_op, reg, 0, exit_func)
-#define INITPARAM(reg) INST(m5_op, reg, 0, initparam_func)
-#define LOADSYMBOL(reg) INST(m5_op, reg, 0, loadsymbol_func)
-#define RESET_STATS(r1, r2) INST(m5_op, r1, r2, resetstats_func)
-#define DUMP_STATS(r1, r2) INST(m5_op, r1, r2, dumpstats_func)
-#define DUMPRST_STATS(r1, r2) INST(m5_op, r1, r2, dumprststats_func)
-#define CHECKPOINT(r1, r2) INST(m5_op, r1, r2, ckpt_func)
-#define READFILE INST(m5_op, 0, 0, readfile_func)
-#define DEBUGBREAK INST(m5_op, 0, 0, debugbreak_func)
-#define SWITCHCPU INST(m5_op, 0, 0, switchcpu_func)
-#define ADDSYMBOL(r1,r2) INST(m5_op, r1, r2, addsymbol_func)
-#define PANIC INST(m5_op, 0, 0, panic_func)
-#define AN_BEGIN(r1) INST(m5_op, r1, 0, anbegin_func)
-#define AN_WAIT(r1,r2) INST(m5_op, r1, r2, anwait_func)
-
- .set noreorder
-
- .align 4
-LEAF(arm)
- ARM(16)
- RET
-END(arm)
-
- .align 4
-LEAF(quiesce)
- QUIESCE
- RET
-END(quiesce)
-
- .align 4
-LEAF(quiesceNs)
- QUIESCENS(16)
- RET
-END(quiesceNs)
-
- .align 4
-LEAF(quiesceCycle)
- QUIESCECYC(16)
- RET
-END(quiesceCycle)
-
- .align 4
-LEAF(quiesceTime)
- QUIESCETIME
- RET
-END(quiesceTime)
-
- .align 4
-LEAF(m5_exit)
- M5EXIT(16)
- RET
-END(m5_exit)
-
- .align 4
-LEAF(m5_initparam)
- INITPARAM(0)
- RET
-END(m5_initparam)
-
- .align 4
-LEAF(m5_loadsymbol)
- LOADSYMBOL(0)
- RET
-END(m5_loadsymbol)
-
- .align 4
-LEAF(m5_reset_stats)
- RESET_STATS(16, 17)
- RET
-END(m5_reset_stats)
-
- .align 4
-LEAF(m5_dump_stats)
- DUMP_STATS(16, 17)
- RET
-END(m5_dump_stats)
-
- .align 4
-LEAF(m5_dumpreset_stats)
- DUMPRST_STATS(16, 17)
- RET
-END(m5_dumpreset_stats)
-
- .align 4
-LEAF(m5_checkpoint)
- CHECKPOINT(16, 17)
- RET
-END(m5_checkpoint)
-
- .align 4
-LEAF(m5_readfile)
- READFILE
- RET
-END(m5_readfile)
-
- .align 4
-LEAF(m5_debugbreak)
- DEBUGBREAK
- RET
-END(m5_debugbreak)
-
- .align 4
-LEAF(m5_switchcpu)
- SWITCHCPU
- RET
-END(m5_switchcpu)
-
- .align 4
-LEAF(m5_addsymbol)
- ADDSYMBOL(16, 17)
- RET
-END(m5_addsymbol)
-
- .align 4
-LEAF(m5_panic)
- PANIC
- RET
-END(m5_panic)
-
-
- .align 4
-LEAF(m5_anbegin)
- AN_BEGIN(16)
- RET
-END(m5_anbegin)
-
-
- .align 4
-LEAF(m5_anwait)
- AN_WAIT(16,17)
- RET
-END(m5_anwait)
-
-
#ifndef __M5OP_H__
#define __M5OP_H__
-#include <asm/types.h>
+#include <stdint.h>
void arm(uint64_t address);
void quiesce(void);
--- /dev/null
+/*
+ * Copyright (c) 2003-2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ * Ali Saidi
+ */
+
+#define m5_op 0x01
+
+#include "m5ops.h"
+
+#define INST(op, ra, rb, func) \
+ .long (((op) << 26) | ((ra) << 21) | ((rb) << 16) | (func))
+
+#define LEAF(func) \
+ .align 3; \
+ .globl func; \
+ .ent func; \
+func:
+
+#define RET \
+ ret ($26)
+
+#define END(func) \
+ .end func
+
+#define ARM(reg) INST(m5_op, reg, 0, arm_func)
+#define QUIESCE INST(m5_op, 0, 0, quiesce_func)
+#define QUIESCENS(r1) INST(m5_op, r1, 0, quiescens_func)
+#define QUIESCECYC(r1) INST(m5_op, r1, 0, quiescecycle_func)
+#define QUIESCETIME INST(m5_op, 0, 0, quiescetime_func)
+#define M5EXIT(reg) INST(m5_op, reg, 0, exit_func)
+#define INITPARAM(reg) INST(m5_op, reg, 0, initparam_func)
+#define LOADSYMBOL(reg) INST(m5_op, reg, 0, loadsymbol_func)
+#define RESET_STATS(r1, r2) INST(m5_op, r1, r2, resetstats_func)
+#define DUMP_STATS(r1, r2) INST(m5_op, r1, r2, dumpstats_func)
+#define DUMPRST_STATS(r1, r2) INST(m5_op, r1, r2, dumprststats_func)
+#define CHECKPOINT(r1, r2) INST(m5_op, r1, r2, ckpt_func)
+#define READFILE INST(m5_op, 0, 0, readfile_func)
+#define DEBUGBREAK INST(m5_op, 0, 0, debugbreak_func)
+#define SWITCHCPU INST(m5_op, 0, 0, switchcpu_func)
+#define ADDSYMBOL(r1,r2) INST(m5_op, r1, r2, addsymbol_func)
+#define PANIC INST(m5_op, 0, 0, panic_func)
+#define AN_BEGIN(r1) INST(m5_op, r1, 0, anbegin_func)
+#define AN_WAIT(r1,r2) INST(m5_op, r1, r2, anwait_func)
+
+ .set noreorder
+
+ .align 4
+LEAF(arm)
+ ARM(16)
+ RET
+END(arm)
+
+ .align 4
+LEAF(quiesce)
+ QUIESCE
+ RET
+END(quiesce)
+
+ .align 4
+LEAF(quiesceNs)
+ QUIESCENS(16)
+ RET
+END(quiesceNs)
+
+ .align 4
+LEAF(quiesceCycle)
+ QUIESCECYC(16)
+ RET
+END(quiesceCycle)
+
+ .align 4
+LEAF(quiesceTime)
+ QUIESCETIME
+ RET
+END(quiesceTime)
+
+ .align 4
+LEAF(m5_exit)
+ M5EXIT(16)
+ RET
+END(m5_exit)
+
+ .align 4
+LEAF(m5_initparam)
+ INITPARAM(0)
+ RET
+END(m5_initparam)
+
+ .align 4
+LEAF(m5_loadsymbol)
+ LOADSYMBOL(0)
+ RET
+END(m5_loadsymbol)
+
+ .align 4
+LEAF(m5_reset_stats)
+ RESET_STATS(16, 17)
+ RET
+END(m5_reset_stats)
+
+ .align 4
+LEAF(m5_dump_stats)
+ DUMP_STATS(16, 17)
+ RET
+END(m5_dump_stats)
+
+ .align 4
+LEAF(m5_dumpreset_stats)
+ DUMPRST_STATS(16, 17)
+ RET
+END(m5_dumpreset_stats)
+
+ .align 4
+LEAF(m5_checkpoint)
+ CHECKPOINT(16, 17)
+ RET
+END(m5_checkpoint)
+
+ .align 4
+LEAF(m5_readfile)
+ READFILE
+ RET
+END(m5_readfile)
+
+ .align 4
+LEAF(m5_debugbreak)
+ DEBUGBREAK
+ RET
+END(m5_debugbreak)
+
+ .align 4
+LEAF(m5_switchcpu)
+ SWITCHCPU
+ RET
+END(m5_switchcpu)
+
+ .align 4
+LEAF(m5_addsymbol)
+ ADDSYMBOL(16, 17)
+ RET
+END(m5_addsymbol)
+
+ .align 4
+LEAF(m5_panic)
+ PANIC
+ RET
+END(m5_panic)
+
+
+ .align 4
+LEAF(m5_anbegin)
+ AN_BEGIN(16)
+ RET
+END(m5_anbegin)
+
+
+ .align 4
+LEAF(m5_anwait)
+ AN_WAIT(16,17)
+ RET
+END(m5_anwait)
+
+
--- /dev/null
+/*
+ * Copyright (c) 2003-2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ * Ali Saidi
+ */
+
+#define m5_op 0x2
+#define m5_op3 0x37
+
+#include "m5ops.h"
+
+#define INST(func, rs1, rs2, rd) \
+ .long (m5_op) << 30 | (rd) << 25 | (m5_op3) << 19 | (func) << 7 | \
+ (rs1) << 14 | (rs2) << 0;
+
+
+#define LEAF(func) \
+ .section ".text"; \
+ .align 4; \
+ .global func; \
+ .type func, #function; \
+func:
+
+#define END(func) \
+ .size func, (.-func)
+
+#define M5EXIT INST(exit_func, 0, 0, 0)
+#define PANIC INST(panic_func, 0, 0, 0)
+
+LEAF(m5_exit)
+ retl
+ M5EXIT
+END(m5_exit)
+
+LEAF(m5_panic)
+ retl
+ PANIC
+END(m5_panic)
+
+
+/* !!!!!! All code below here just panics !!!!!! */
+LEAF(arm)
+ retl
+ PANIC
+END(arm)
+
+LEAF(quiesce)
+ retl
+ PANIC
+END(quiesce)
+
+LEAF(quiesceNs)
+ retl
+ PANIC
+END(quiesceNs)
+
+LEAF(quiesceCycle)
+ retl
+ PANIC
+END(quiesceCycle)
+
+LEAF(quiesceTime)
+ retl
+ PANIC
+END(quiesceTime)
+
+LEAF(m5_initparam)
+ retl
+ PANIC
+END(m5_initparam)
+
+LEAF(m5_loadsymbol)
+ retl
+ PANIC
+END(m5_loadsymbol)
+
+LEAF(m5_reset_stats)
+ retl
+ PANIC
+END(m5_reset_stats)
+
+LEAF(m5_dump_stats)
+ retl
+ PANIC
+END(m5_dump_stats)
+
+LEAF(m5_dumpreset_stats)
+ retl
+ PANIC
+END(m5_dumpreset_stats)
+
+LEAF(m5_checkpoint)
+ retl
+ PANIC
+END(m5_checkpoint)
+
+LEAF(m5_readfile)
+ retl
+ PANIC
+END(m5_readfile)
+
+LEAF(m5_debugbreak)
+ retl
+ PANIC
+END(m5_debugbreak)
+
+LEAF(m5_switchcpu)
+ retl
+ PANIC
+END(m5_switchcpu)
+
+LEAF(m5_addsymbol)
+ retl
+ PANIC
+END(m5_addsymbol)
+
+LEAF(m5_anbegin)
+ retl
+ PANIC
+END(m5_anbegin)
+
+LEAF(m5_anwait)
+ retl
+ PANIC
+END(m5_anwait)
+
+
--- /dev/null
+/*
+ * Copyright (c) 2003-2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ * Ali Saidi
+ */
+
+#define arm_func 0x00
+#define quiesce_func 0x01
+#define quiescens_func 0x02
+#define quiescecycle_func 0x03
+#define quiescetime_func 0x04
+#define ivlb 0x10 // obsolete
+#define ivle 0x11 // obsolete
+#define exit_old_func 0x20 // deprecated!
+#define exit_func 0x21
+#define initparam_func 0x30
+#define loadsymbol_func 0x31
+#define resetstats_func 0x40
+#define dumpstats_func 0x41
+#define dumprststats_func 0x42
+#define ckpt_func 0x43
+#define readfile_func 0x50
+#define debugbreak_func 0x51
+#define switchcpu_func 0x52
+#define addsymbol_func 0x53
+#define panic_func 0x54
+#define anbegin_func 0x55
+#define anwait_func 0x56
+
projects / gem5.git / commitdiff