;; instruction which allows full access to the entire address space,
;; but we do not do so at present.
-(define_attr "length" ""
+(define_attr "length" ""
(cond [(eq_attr "type" "branch")
(cond [(lt (abs (minus (match_dup 1) (plus (pc) (const_int 4))))
(const_int 131072))
;; Does the instruction have a mandatory delay slot?
;; The 3900, is (mostly) mips1, but does not have a mandatory load delay
-;; slot.
+;; slot.
(define_attr "dslot" "no,yes"
(if_then_else (ior (eq_attr "type" "branch,jump,call,xfer,hilo,fcmp")
(and (eq_attr "type" "load")
;; (define_function_unit "memory" 1 0 (eq_attr "type" "load") 3 0)
;; (define_function_unit "memory" 1 0 (eq_attr "type" "store") 1 0)
-;;
+;;
;; (define_function_unit "fp_comp" 1 0 (eq_attr "type" "fcmp") 2 0)
-;;
+;;
;; (define_function_unit "transfer" 1 0 (eq_attr "type" "xfer") 2 0)
;; (define_function_unit "transfer" 1 0 (eq_attr "type" "hilo") 3 0)
-;;
+;;
;; (define_function_unit "imuldiv" 1 1 (eq_attr "type" "imul") 17 0)
;; (define_function_unit "imuldiv" 1 1 (eq_attr "type" "idiv") 38 0)
-;;
+;;
;; (define_function_unit "adder" 1 1 (eq_attr "type" "fadd") 4 0)
;; (define_function_unit "adder" 1 1 (eq_attr "type" "fabs,fneg") 2 0)
-;;
+;;
;; (define_function_unit "mult" 1 1 (and (eq_attr "type" "fmul") (eq_attr "mode" "SF")) 7 0)
;; (define_function_unit "mult" 1 1 (and (eq_attr "type" "fmul") (eq_attr "mode" "DF")) 8 0)
-;;
+;;
;; (define_function_unit "divide" 1 1 (and (eq_attr "type" "fdiv") (eq_attr "mode" "SF")) 23 0)
;; (define_function_unit "divide" 1 1 (and (eq_attr "type" "fdiv") (eq_attr "mode" "DF")) 36 0)
-;;
+;;
;; (define_function_unit "sqrt" 1 1 (and (eq_attr "type" "fsqrt") (eq_attr "mode" "SF")) 54 0)
;; (define_function_unit "sqrt" 1 1 (and (eq_attr "type" "fsqrt") (eq_attr "mode" "DF")) 112 0)
\f
(const_int 4)
(const_int 8))
(const_int 4)])])
-
+
\f
;;
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"
{
- if (TARGET_MIPS4300)
+ if (!TARGET_MIPS4300)
emit_insn (gen_muldf3_internal (operands[0], operands[1], operands[2]));
else
emit_insn (gen_muldf3_r4300 (operands[0], operands[1], operands[2]));
{
if (GENERATE_MULT3)
output_asm_insn (\"dmult\\t%0,%1,%2\", operands);
- else
+ else
{
rtx xoperands[10];
(minus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
(match_operand:SF 2 "register_operand" "f"))
(match_operand:SF 3 "register_operand" "f")))]
-
+
"ISA_HAS_FP4 && TARGET_HARD_FLOAT"
"msub.s\\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
(BITMASK_HIGH, SImode))),
GEN_INT (0x6)));
}
-
+
DONE;
}")
GEN_INT (BITMASK_HIGH)),
GEN_INT (0x6)));
}
-
+
DONE;
}")
GEN_INT (0),
GEN_INT (0x7)));
}
-
+
DONE;
}")
GEN_INT (0),
GEN_INT (0x7)));
}
-
+
DONE;
}")
have_dep_anti = 1;
if (! have_dep_anti)
{
- /* No branch delay slots on mips16. */
+ /* No branch delay slots on mips16. */
if (which_alternative == 1)
return \"%(bnez\\t%0,1f\\n\\tbreak\\t%2\\n%~1:%)\";
else
(BITMASK_HIGH, SImode))),
GEN_INT (0x6)));
}
-
+
DONE;
}")
(define_expand "divdi3"
[(set (match_operand:DI 0 "register_operand" "=l")
(div:DI (match_operand:DI 1 "se_register_operand" "d")
- (match_operand:DI 2 "se_register_operand" "d")))
+ (match_operand:DI 2 "se_register_operand" "d")))
(clobber (match_scratch:DI 3 "=h"))
(clobber (match_scratch:DI 4 "=a"))]
"TARGET_64BIT && !optimize"
GEN_INT (BITMASK_HIGH)),
GEN_INT (0x6)));
}
-
+
DONE;
}")
(BITMASK_HIGH, SImode))),
GEN_INT (0x6)));
}
-
+
DONE;
}")
GEN_INT (BITMASK_HIGH)),
GEN_INT (0x6)));
}
-
+
DONE;
}")
GEN_INT (0),
GEN_INT (0x7)));
}
-
+
DONE;
}")
GEN_INT (0),
GEN_INT (0x7)));
}
-
+
DONE;
}")
GEN_INT (0),
GEN_INT (0x7)));
}
-
+
DONE;
}")
GEN_INT (0),
GEN_INT (0x7)));
}
-
+
DONE;
}")
return \"%(bltzl\\t%1,1f\\n\\tsubu\\t%0,%z2,%0\\n%~1:%)\";
else
return \"bgez\\t%1,1f%#\\n\\tsubu\\t%0,%z2,%0\\n%~1:\";
- }
+ }
else
return \"%(bgez\\t%1,1f\\n\\tmove\\t%0,%1\\n\\tsubu\\t%0,%z2,%0\\n%~1:%)\";
}"
dslots_jump_total++;
dslots_jump_filled++;
operands[2] = const0_rtx;
-
+
if (GET_CODE (operands[1]) == REG)
regno1 = REGNO (operands[1]);
- else
+ else
regno1 = REGNO (XEXP (operands[1], 0));
if (REGNO (operands[0]) == regno1)
{
if (TARGET_MIPS16)
return \"dsll\\t%0,%1,56\;dsra\\t%0,56\";
- return \"andi\\t%0,%1,0x00ff\";
+ return \"andi\\t%0,%1,0x00ff\";
}"
[(set_attr "type" "darith")
(set_attr "mode" "QI")
[(set_attr "type" "darith")
(set_attr "mode" "SI")
(set_attr "length" "8")])
-
+
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=d")
(truncate:SI (lshiftrt:DI (match_operand:DI 1 "se_register_operand" "d")
"
{
/* If the field does not start on a byte boundary, then fail. */
- if (INTVAL (operands[3]) % 8 != 0)
+ if (INTVAL (operands[3]) % 8 != 0)
FAIL;
/* MIPS I and MIPS II can only handle a 32bit field. */
"
{
/* If the field does not start on a byte boundary, then fail. */
- if (INTVAL (operands[3]) % 8 != 0)
+ if (INTVAL (operands[3]) % 8 != 0)
FAIL;
/* MIPS I and MIPS II can only handle a 32bit field. */
"
{
/* If the field does not start on a byte boundary, then fail. */
- if (INTVAL (operands[2]) % 8 != 0)
+ if (INTVAL (operands[2]) % 8 != 0)
FAIL;
/* MIPS I and MIPS II can only handle a 32bit field. */
"
{
rtx scratch = gen_rtx_REG (DImode,
- (REGNO (operands[0]) == REGNO (operands[2])
+ (REGNO (operands[0]) == REGNO (operands[2])
? REGNO (operands[2]) + 1
: REGNO (operands[2])));
(match_operand:SI 2 "register_operand" "d")))
(clobber (match_operand:SI 3 "register_operand" "=d"))]
"!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
- "*
+ "*
{
operands[4] = const0_rtx;
dslots_jump_total += 3;
(match_operand:SI 2 "register_operand" "d")))
(clobber (match_operand:SI 3 "register_operand" "=d"))]
"!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
- "*
+ "*
{
operands[4] = const0_rtx;
dslots_jump_total += 3;
(match_operand:SI 2 "register_operand" "d")))
(clobber (match_operand:SI 3 "register_operand" "=d"))]
"!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
- "*
+ "*
{
operands[4] = const0_rtx;
dslots_jump_total += 3;
(define_insn "branch_fp"
[(set (pc)
- (if_then_else
+ (if_then_else
(match_operator:CC 0 "cmp_op"
[(match_operand:CC 2 "register_operand" "z")
(const_int 0)])
(define_insn "branch_fp_inverted"
[(set (pc)
- (if_then_else
+ (if_then_else
(match_operator:CC 0 "cmp_op"
[(match_operand:CC 2 "register_operand" "z")
(const_int 0)])
(define_insn "branch_zero"
[(set (pc)
- (if_then_else
+ (if_then_else
(match_operator:SI 0 "cmp_op"
[(match_operand:SI 2 "register_operand" "d")
(const_int 0)])
(define_insn "branch_zero_inverted"
[(set (pc)
- (if_then_else
+ (if_then_else
(match_operator:SI 0 "cmp_op"
[(match_operand:SI 2 "register_operand" "d")
(const_int 0)])
(define_insn "branch_zero_di"
[(set (pc)
- (if_then_else
+ (if_then_else
(match_operator:DI 0 "cmp_op"
[(match_operand:DI 2 "se_register_operand" "d")
(const_int 0)])
(define_insn "branch_zero_di_inverted"
[(set (pc)
- (if_then_else
+ (if_then_else
(match_operator:DI 0 "cmp_op"
[(match_operand:DI 2 "se_register_operand" "d")
(const_int 0)])
(define_insn "branch_equality"
[(set (pc)
- (if_then_else
+ (if_then_else
(match_operator:SI 0 "equality_op"
[(match_operand:SI 2 "register_operand" "d")
(match_operand:SI 3 "register_operand" "d")])
(define_insn "branch_equality_di"
[(set (pc)
- (if_then_else
+ (if_then_else
(match_operator:DI 0 "equality_op"
[(match_operand:DI 2 "se_register_operand" "d")
(match_operand:DI 3 "se_register_operand" "d")])
(define_insn "branch_equality_inverted"
[(set (pc)
- (if_then_else
+ (if_then_else
(match_operator:SI 0 "equality_op"
[(match_operand:SI 2 "register_operand" "d")
(match_operand:SI 3 "register_operand" "d")])
(define_insn "branch_equality_di_inverted"
[(set (pc)
- (if_then_else
+ (if_then_else
(match_operator:DI 0 "equality_op"
[(match_operand:DI 2 "se_register_operand" "d")
(match_operand:DI 3 "se_register_operand" "d")])
in a switch table, then used in a `j' instruction. */
else if (mips_abi != ABI_32 && mips_abi != ABI_O64)
return \"%*b\\t%l0\";
- else
+ else
return \"%*j\\t%l0\";
}"
[(set_attr "type" "jump")
/* Do the PIC jump. */
if (Pmode != DImode)
- emit_jump_insn (gen_casesi_internal (reg, operands[3],
+ emit_jump_insn (gen_casesi_internal (reg, operands[3],
gen_reg_rtx (SImode)));
else
- emit_jump_insn (gen_casesi_internal_di (reg, operands[3],
+ emit_jump_insn (gen_casesi_internal_di (reg, operands[3],
gen_reg_rtx (DImode)));
DONE;
(define_insn "casesi_internal_di"
[(set (pc)
- (mem:DI (plus:DI (sign_extend:DI
+ (mem:DI (plus:DI (sign_extend:DI
(mult:SI (match_operand:SI 0 "register_operand" "d")
(const_int 4)))
(label_ref (match_operand 1 "" "")))))
"TARGET_ABICALLS && Pmode == DImode"
"")
-;; For o32/n32/n64, we need to arrange for longjmp to put the
+;; For o32/n32/n64, we need to arrange for longjmp to put the
;; target address in t9 so that we can use it for loading $gp.
(define_expand "builtin_longjmp"
}"
[(set_attr "type" "jump")
(set_attr "mode" "none")])
-
+
;; When generating embedded PIC code we need to get the address of the
;; current function. This specialized instruction does just that.
(call (mem:SI (match_operand:SI 1 "register_operand" "r"))
(match_operand 2 "" "i")))
(clobber (match_operand:SI 3 "register_operand" "=d"))]
- "!TARGET_MIPS16
+ "!TARGET_MIPS16
&& !(Pmode == DImode) && !TARGET_ABICALLS && TARGET_LONG_CALLS"
"%*jal\\t%3,%1"
[(set_attr "type" "call")
(call (mem:DI (match_operand:DI 1 "se_register_operand" "r"))
(match_operand 2 "" "i")))
(clobber (match_operand:SI 3 "register_operand" "=d"))]
- "!TARGET_MIPS16
+ "!TARGET_MIPS16
&& Pmode == DImode && !TARGET_ABICALLS && TARGET_LONG_CALLS"
"%*jal\\t%3,%1"
[(set_attr "type" "call")
;; operands[0] = gen_reg_rtx (SImode);
;; operands[1] = gen_rtx_MEM (SImode, stack_pointer_rtx);
;; MEM_VOLATILE_P (operands[1]) = TRUE;
-;;
+;;
;; /* fall through and generate default code */
;; }")
;;
(if_then_else:DI (match_dup 5)
(match_operand:DI 2 "se_reg_or_0_operand" "")
(match_operand:DI 3 "se_reg_or_0_operand" "")))]
- "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
+ "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
"
{
gen_conditional_move (operands);