techlibs/greenpak4/cells_map.v: Harmonize whitespace within lut module

diff --git a/techlibs/greenpak4/cells_map.v b/techlibs/greenpak4/cells_map.v
index b971a51faa929bacaf2d2fda581b5220662c22d1..51c85183d29cb4fc63bb25ba7e26b9052fbdbfdc 100644 (file)
--- a/techlibs/greenpak4/cells_map.v
+++ b/techlibs/greenpak4/cells_map.v
@@ -112,14 +112,14 @@ module GP_OBUFT(input IN, input OE, output OUT);
 endmodule
 
 module \$lut (A, Y);
-  parameter WIDTH = 0;
-  parameter LUT = 0;
+       parameter WIDTH = 0;
+       parameter LUT = 0;
 
-  input [WIDTH-1:0] A;
-  output Y;
+       input [WIDTH-1:0] A;
+       output Y;
 
-  generate
-    if (WIDTH == 1) begin
+       generate
+               if (WIDTH == 1) begin
                if(LUT == 2'b01) begin
                        GP_INV _TECHMAP_REPLACE_ (.OUT(Y), .IN(A[0]) );
                end
@@ -127,22 +127,22 @@ module \$lut (A, Y);
                        GP_2LUT #(.INIT({2'b00, LUT})) _TECHMAP_REPLACE_ (.OUT(Y),
                                .IN0(A[0]), .IN1(1'b0));
                end
-    end else
-    if (WIDTH == 2) begin
-      GP_2LUT #(.INIT(LUT)) _TECHMAP_REPLACE_ (.OUT(Y),
-       .IN0(A[0]), .IN1(A[1]));
-    end else
-    if (WIDTH == 3) begin
-      GP_3LUT #(.INIT(LUT)) _TECHMAP_REPLACE_ (.OUT(Y),
-       .IN0(A[0]), .IN1(A[1]), .IN2(A[2]));
-    end else
-    if (WIDTH == 4) begin
-      GP_4LUT #(.INIT(LUT)) _TECHMAP_REPLACE_ (.OUT(Y),
-       .IN0(A[0]), .IN1(A[1]), .IN2(A[2]), .IN3(A[3]));
-    end else begin
-      wire _TECHMAP_FAIL_ = 1;
-    end
-  endgenerate
+               end else
+               if (WIDTH == 2) begin
+                       GP_2LUT #(.INIT(LUT)) _TECHMAP_REPLACE_ (.OUT(Y),
+                               .IN0(A[0]), .IN1(A[1]));
+               end else
+               if (WIDTH == 3) begin
+                       GP_3LUT #(.INIT(LUT)) _TECHMAP_REPLACE_ (.OUT(Y),
+                               .IN0(A[0]), .IN1(A[1]), .IN2(A[2]));
+               end else
+               if (WIDTH == 4) begin
+                       GP_4LUT #(.INIT(LUT)) _TECHMAP_REPLACE_ (.OUT(Y),
+                               .IN0(A[0]), .IN1(A[1]), .IN2(A[2]), .IN3(A[3]));
+               end else begin
+                       wire _TECHMAP_FAIL_ = 1;
+               end
+       endgenerate
 endmodule
 
 module \$__COUNT_ (CE, CLK, OUT, POUT, RST, UP);