simulator core object.
+Mon May 5 11:16:12 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * sim-config.h (FORCED_ALIGNMENT): New alignment option -
+ addresses are masked forcing them to be correctly aligned.
+ (WITH_ALIGNMENT): Make NONSTRICT_ALIGNMENT the default.
+ * sim-config.c (config_alignment_to_a): Update.
+
+ * sim-core.h (sim_cpu_core): New data type contains cpu specific
+ core data.
+ * sim-base.h (CPU_CORE): Add cpu specific core data to cpu base
+ type.
+ * sim-core.c (sim_core_attach): Add CPU argument. Ready for
+ processor specific core maps.
+ (sim_core_map_attach): Copy the core map data to each of the
+ processor specific core data structures.
+ * sim-core.c (sim_core_find_mapping): Update.
+
+ * sim-n-core.h (sim_core_read_N, sim_core_write_N): Rename.
+ (sim_core_write_aligned_N, sim_core_write_aligned_N): New names.
+ (sim_core_write_unaligned_N, sim_core_write_unaligned_N): New
+ alternatives that handle unaligned addresses.
+ (sim_core_{read,write}_{,un}aligned_N): Drop SIM_DESC arg, replace
+ with just CPU arg.
+ * cgen-utils.c (sim_disassemble_insn): Update.
+
Mon May 5 13:19:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
* sim-trace.h (TRACE_FPU_IDX): Add Floating-point specific
SIM_DESC state;
#define CPU_STATE(cpu) ((cpu)->base.state)
+ /* Processor specific core data */
+#define CPU_CORE(cpu) (& (cpu)->base.core)
+ sim_cpu_core core;
+
/* Trace data. See sim-trace.h. */
TRACE_DATA trace_data;
#define CPU_TRACE_DATA(cpu) (& (cpu)->base.trace_data)
STATIC_INLINE_SIM_CORE\
(void)
sim_core_map_attach(SIM_DESC sd,
- sim_core_map *access_map,
- attach_type attach,
- int space,
- unsigned_word addr,
- unsigned nr_bytes, /* host limited */
- device *client, /*callback/default*/
- void *buffer, /*raw_memory*/
- int free_buffer) /*raw_memory*/
+ sim_core_map *access_map,
+ attach_type attach,
+ int space,
+ unsigned_word addr,
+ unsigned nr_bytes, /* host limited */
+ device *client, /*callback/default*/
+ void *buffer, /*raw_memory*/
+ int free_buffer) /*raw_memory*/
{
/* find the insertion point for this additional mapping and then
insert */
INLINE_SIM_CORE\
(void)
sim_core_attach(SIM_DESC sd,
- attach_type attach,
- access_type access,
- int space,
- unsigned_word addr,
- unsigned nr_bytes, /* host limited */
- device *client,
- void *optional_buffer)
+ sim_cpu *cpu,
+ attach_type attach,
+ access_type access,
+ int space,
+ unsigned_word addr,
+ unsigned nr_bytes, /* host limited */
+ device *client,
+ void *optional_buffer)
{
sim_core *memory = STATE_CORE(sd);
sim_core_maps map;
void *buffer;
int buffer_freed;
+ int i;
+
+ /* check for for attempt to use unimplemented per-processor core map */
+ if (cpu != NULL)
+ sim_io_error (sd, "sim_core_map_attach - processor specific memory map not yet supported");
+
if ((access & access_read_write_exec) == 0
|| (access & ~access_read_write_exec) != 0) {
#if (WITH_DEVICES)
break;
}
}
+
+ /* Just copy this map to each of the processor specific data structures.
+ FIXME - later this will be replaced by true processor specific
+ maps. */
+ for (i = 0; i < MAX_NR_PROCESSORS; i++)
+ *CPU_CORE (STATE_CPU (sd, i)) = *STATE_CORE (sd);
}
STATIC_INLINE_SIM_CORE\
(sim_core_mapping *)
-sim_core_find_mapping(SIM_DESC sd,
+sim_core_find_mapping(sim_core *core,
sim_core_maps map,
unsigned_word addr,
unsigned nr_bytes,
- int abort, /*either 0 or 1 - helps inline */
- sim_cpu *cpu,
+ int abort, /*either 0 or 1 - hint to inline/-O */
+ sim_cpu *cpu, /* abort => cpu != NULL */
sim_cia cia)
{
- sim_core_mapping *mapping = STATE_CORE (sd)->map[map].first;
- SIM_ASSERT((addr & (nr_bytes - 1)) == 0); /* must be aligned */
- SIM_ASSERT((addr + (nr_bytes - 1)) >= addr); /* must not wrap */
- while (mapping != NULL) {
- if (addr >= mapping->base
- && (addr + (nr_bytes - 1)) <= mapping->bound)
- return mapping;
- mapping = mapping->next;
- }
+ sim_core_mapping *mapping = core->map[map].first;
+ ASSERT ((addr & (nr_bytes - 1)) == 0); /* must be aligned */
+ ASSERT ((addr + (nr_bytes - 1)) >= addr); /* must not wrap */
+ ASSERT (!abort || cpu != NULL); /* abort needs a non null CPU */
+ while (mapping != NULL)
+ {
+ if (addr >= mapping->base
+ && (addr + (nr_bytes - 1)) <= mapping->bound)
+ return mapping;
+ mapping = mapping->next;
+ }
if (abort)
- sim_io_error (sd, "access to unmaped address 0x%lx (%d bytes)\n",
- (unsigned long) addr, nr_bytes);
+ {
+ if (cpu == NULL)
+ sim_io_error (NULL, "sim_core_find_map - internal error - can not abort without a processor");
+ else
+ sim_io_error (CPU_STATE (cpu),
+ "access to unmaped address 0x%lx (%d bytes)\n",
+ (unsigned long) addr, nr_bytes);
+ }
return NULL;
}
while (count < len) {
unsigned_word raddr = addr + count;
sim_core_mapping *mapping =
- sim_core_find_mapping(sd, map,
+ sim_core_find_mapping(STATE_CORE (sd), map,
raddr, 1,
0, NULL, NULL_CIA); /*dont-abort*/
if (mapping == NULL)
unsigned count = 0;
while (count < len) {
unsigned_word raddr = addr + count;
- sim_core_mapping *mapping = sim_core_find_mapping(sd, map,
+ sim_core_mapping *mapping = sim_core_find_mapping(STATE_CORE (sd), map,
raddr, 1,
0, NULL, NULL_CIA); /*dont-abort*/
if (mapping == NULL)
void *buffer;
/* callback map */
device *device;
+ /* tracing */
+ int trace;
/* growth */
sim_core_mapping *next;
};
nr_sim_core_maps,
} sim_core_maps;
+
+/* Main core structure */
+
typedef struct _sim_core sim_core;
struct _sim_core {
int trace;
};
+/* Per CPU distributed component of the core */
+
+typedef sim_core sim_cpu_core;
+
+
/* Install the "core" module. */
EXTERN_SIM_CORE\
sim_core_uninstall (SIM_DESC sd);
+
/* initialize */
EXTERN_SIM_CORE\
(SIM_DESC sd);
+
/* tracing */
INLINE_SIM_CORE\
-/* Create a memory space within the core. */
+/* Create a memory space within the core.
+
+ The CPU option (when non NULL) specifes the single processor that
+ the memory space is to be attached to. (unimplemented) */
INLINE_SIM_CORE\
(void) sim_core_attach
(SIM_DESC sd,
+ sim_cpu *cpu,
attach_type attach,
access_type access,
int address_space,
/* Variable sized read/write
- Transfer (zero) a variable size block of data between the host and
- target (possibly byte swapping it). Should any problems occure,
- the number of bytes actually transfered is returned. */
+ Transfer a variable sized block of raw data between the host and
+ target. Should any problems occure, the number of bytes
+ successfully transfered is returned. */
INLINE_SIM_CORE\
(unsigned) sim_core_read_buffer
unsigned nr_bytes);
-/* Fixed sized read/write
+/* Fixed sized, processor oriented, read/write.
Transfer a fixed amout of memory between the host and target. The
- memory always being translated and the operation always aborting
- should a problem occure */
-
-#define DECLARE_SIM_CORE_WRITE_N(N) \
+ data transfered is translated from/to host to/from target byte
+ order. Should the transfer fail, the operation shall abort (no
+ return). The aligned alternative makes the assumption that that
+ the address is N byte aligned (no alignment checks are made). The
+ unaligned alternative checks the address for correct byte
+ alignment. Action, as defined by WITH_ALIGNMENT, being taken
+ should the check fail. */
+
+#define DECLARE_SIM_CORE_WRITE_N(ALIGNMENT,N) \
INLINE_SIM_CORE\
-(void) sim_core_write_##N \
-(SIM_DESC sd, \
+(void) sim_core_write_##ALIGNMENT##_##N \
+(sim_cpu *cpu, \
+ sim_cia cia, \
sim_core_maps map, \
unsigned_word addr, \
unsigned_##N val);
-DECLARE_SIM_CORE_WRITE_N(1)
-DECLARE_SIM_CORE_WRITE_N(2)
-DECLARE_SIM_CORE_WRITE_N(4)
-DECLARE_SIM_CORE_WRITE_N(8)
-DECLARE_SIM_CORE_WRITE_N(word)
+DECLARE_SIM_CORE_WRITE_N(aligned,1)
+DECLARE_SIM_CORE_WRITE_N(aligned,2)
+DECLARE_SIM_CORE_WRITE_N(aligned,4)
+DECLARE_SIM_CORE_WRITE_N(aligned,8)
+DECLARE_SIM_CORE_WRITE_N(aligned,word)
+
+DECLARE_SIM_CORE_WRITE_N(unaligned,1)
+DECLARE_SIM_CORE_WRITE_N(unaligned,2)
+DECLARE_SIM_CORE_WRITE_N(unaligned,4)
+DECLARE_SIM_CORE_WRITE_N(unaligned,8)
+DECLARE_SIM_CORE_WRITE_N(unaligned,word)
+
+#define sim_core_write_1 sim_core_write_aligned_1
+#define sim_core_write_2 sim_core_write_aligned_2
+#define sim_core_write_4 sim_core_write_aligned_4
+#define sim_core_write_8 sim_core_write_aligned_8
#undef DECLARE_SIM_CORE_WRITE_N
-#define DECLARE_SIM_CORE_READ_N(N) \
+#define DECLARE_SIM_CORE_READ_N(ALIGNMENT,N) \
INLINE_SIM_CORE\
-(unsigned_##N) sim_core_read_##N \
-(SIM_DESC sd, \
+(unsigned_##N) sim_core_read_##ALIGNMENT##_##N \
+(sim_cpu *cpu, \
+ sim_cia cia, \
sim_core_maps map, \
unsigned_word addr);
-DECLARE_SIM_CORE_READ_N(1)
-DECLARE_SIM_CORE_READ_N(2)
-DECLARE_SIM_CORE_READ_N(4)
-DECLARE_SIM_CORE_READ_N(8)
-DECLARE_SIM_CORE_READ_N(word)
+DECLARE_SIM_CORE_READ_N(aligned,1)
+DECLARE_SIM_CORE_READ_N(aligned,2)
+DECLARE_SIM_CORE_READ_N(aligned,4)
+DECLARE_SIM_CORE_READ_N(aligned,8)
+DECLARE_SIM_CORE_READ_N(aligned,word)
+
+DECLARE_SIM_CORE_READ_N(unaligned,1)
+DECLARE_SIM_CORE_READ_N(unaligned,2)
+DECLARE_SIM_CORE_READ_N(unaligned,4)
+DECLARE_SIM_CORE_READ_N(unaligned,8)
+DECLARE_SIM_CORE_READ_N(unaligned,word)
+
+#define sim_core_read_1 sim_core_read_aligned_1
+#define sim_core_read_2 sim_core_read_aligned_2
+#define sim_core_read_4 sim_core_read_aligned_4
+#define sim_core_read_8 sim_core_read_aligned_8
#undef DECLARE_SIM_CORE_READ_N
#define T2H_N XCONCAT2(T2H_,N)
#define H2T_N XCONCAT2(H2T_,N)
-#define sim_core_read_N XCONCAT2(sim_core_read_,N)
-#define sim_core_write_N XCONCAT2(sim_core_write_,N)
+#define sim_core_read_aligned_N XCONCAT2(sim_core_read_aligned_,N)
+#define sim_core_write_aligned_N XCONCAT2(sim_core_write_aligned_,N)
+#define sim_core_read_unaligned_N XCONCAT2(sim_core_read_unaligned_,N)
+#define sim_core_write_unaligned_N XCONCAT2(sim_core_write_unaligned_,N)
INLINE_SIM_CORE(unsigned_N)
-sim_core_read_N(SIM_DESC sd,
- sim_core_maps map,
- unsigned_word addr,
- sim_cpu *cpu,
- sim_cia cia)
+sim_core_read_aligned_N(sim_cpu *cpu,
+ sim_cia cia,
+ sim_core_maps map,
+ unsigned_word addr)
{
unsigned_N val;
- sim_core_mapping *mapping = sim_core_find_mapping (sd, map,
+ sim_core_mapping *mapping = sim_core_find_mapping (CPU_CORE (cpu), map,
addr,
sizeof (unsigned_N),
1,
else
#endif
val = T2H_N (*(unsigned_N*) sim_core_translate (mapping, addr));
- if (STATE_CORE (sd)->trace)
- trace_printf (sd, cpu, "sim-n-core.c:%d: read-%d %s:0x%08lx -> 0x%lx\n",
+ if (TRACE_P (cpu, TRACE_CORE_IDX))
+ trace_printf (CPU_STATE (cpu), cpu,
+ "sim-n-core.c:%d: read-%d %s:0x%08lx -> 0x%lx\n",
__LINE__,
sizeof (unsigned_N),
sim_core_map_to_str (map),
}
+INLINE_SIM_CORE(unsigned_N)
+sim_core_read_unaligned_N(sim_cpu *cpu,
+ sim_cia cia,
+ sim_core_maps map,
+ unsigned_word addr)
+{
+ int alignment = sizeof (unsigned_N) - 1;
+ /* if hardwired to forced alignment just do it */
+ if (WITH_ALIGNMENT == FORCED_ALIGNMENT)
+ return sim_core_read_aligned_N (cpu, cia, map, addr & ~alignment);
+ else if ((addr & alignment) == 0)
+ return sim_core_read_aligned_N (cpu, cia, map, addr);
+ else
+ switch (CURRENT_ALIGNMENT)
+ {
+ case STRICT_ALIGNMENT:
+ /* FIXME - notify abort handler */
+ sim_io_error (CPU_STATE (cpu), "read-%d - misaligned access to 0x%lx",
+ sizeof (unsigned_N), (unsigned long) addr);
+ return -1;
+ case NONSTRICT_ALIGNMENT:
+ {
+ unsigned_N val;
+ if (sim_core_read_buffer (CPU_STATE (cpu), map, &val, addr,
+ sizeof(unsigned_N))
+ != sizeof(unsigned_N))
+ sim_io_error(CPU_STATE (cpu), "misaligned %d byte read to 0x%lx failed",
+ sizeof(unsigned_N), (unsigned long) addr);
+ val = T2H_N(val);
+ return val;
+ }
+ case FORCED_ALIGNMENT:
+ return sim_core_read_aligned_N (cpu, cia, map, addr & ~alignment);
+ case MIXED_ALIGNMENT:
+ sim_io_error (CPU_STATE (cpu), "internal error - sim_core_read_unaligned_N - mixed alignment");
+ return 0;
+ default:
+ sim_io_error (CPU_STATE (cpu), "internal error - sim_core_read_unaligned_N - bad switch");
+ return 0;
+ }
+}
+
INLINE_SIM_CORE(void)
-sim_core_write_N(SIM_DESC sd,
- sim_core_maps map,
- unsigned_word addr,
- unsigned_N val,
- sim_cpu *cpu,
- sim_cia cia)
+sim_core_write_aligned_N(sim_cpu *cpu,
+ sim_cia cia,
+ sim_core_maps map,
+ unsigned_word addr,
+ unsigned_N val)
{
- sim_core_mapping *mapping = sim_core_find_mapping(sd, map,
+ sim_core_mapping *mapping = sim_core_find_mapping(CPU_CORE (cpu), map,
addr,
sizeof (unsigned_N),
1,
else
#endif
*(unsigned_N*) sim_core_translate (mapping, addr) = H2T_N (val);
- if (STATE_CORE (sd)->trace)
- trace_printf (sd, cpu, "sim-n-core.c:%d: write-%d %s:0x%08lx <- 0x%lx\n",
+ if (TRACE_P (cpu, TRACE_CORE_IDX))
+ trace_printf (CPU_STATE (cpu), cpu,
+ "sim-n-core.c:%d: write-%d %s:0x%08lx <- 0x%lx\n",
__LINE__,
sizeof (unsigned_N),
sim_core_map_to_str (map),
}
+INLINE_SIM_CORE(void)
+sim_core_write_unaligned_N(sim_cpu *cpu,
+ sim_cia cia,
+ sim_core_maps map,
+ unsigned_word addr,
+ unsigned_N val)
+{
+ int alignment = sizeof (unsigned_N) - 1;
+ /* if hardwired to forced alignment just do it */
+ if (WITH_ALIGNMENT == FORCED_ALIGNMENT)
+ sim_core_write_aligned_N (cpu, cia, map, addr & ~alignment, val);
+ else if ((addr & alignment) == 0)
+ sim_core_write_aligned_N (cpu, cia, map, addr, val);
+ else
+ switch (CURRENT_ALIGNMENT)
+ {
+ case STRICT_ALIGNMENT:
+ /* FIXME - notify abort handler */
+ sim_io_error (CPU_STATE (cpu),
+ "write-%d - misaligned access to 0x%lx",
+ sizeof (unsigned_N), (unsigned long) addr);
+ break;
+ case NONSTRICT_ALIGNMENT:
+ {
+ val = T2H_N(val);
+ if (sim_core_write_buffer (CPU_STATE (cpu), map, &val, addr,
+ sizeof(unsigned_N))
+ != sizeof(unsigned_N))
+ sim_io_error(CPU_STATE (cpu),
+ "misaligned %d byte read to 0x%lx failed",
+ sizeof(unsigned_N), (unsigned long) addr);
+ break;
+ }
+ case FORCED_ALIGNMENT:
+ sim_core_write_aligned_N (cpu, cia, map, addr & ~alignment, val);
+ case MIXED_ALIGNMENT:
+ sim_io_error (CPU_STATE (cpu), "internal error - sim_core_write_unaligned_N - mixed alignment");
+ break;
+ default:
+ sim_io_error (CPU_STATE (cpu), "internal error - sim_core_write_unaligned_N - bad switch");
+ break;
+ }
+}
+
+
/* NOTE: see start of file for #define of these macros */
#undef unsigned_N
#undef T2H_N
#undef H2T_N
-#undef sim_core_read_N
-#undef sim_core_write_N
+#undef sim_core_read_aligned_N
+#undef sim_core_write_aligned_N
+#undef sim_core_read_unaligned_N
+#undef sim_core_write_unaligned_N
+Mon May 5 12:45:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * sim-if.c (sim_open): Update to reflect changes to core in
+ ../common/.
+ * mem-ops.h (GETMEMQI, GETMEMHI, GETMEMSI, GETMEMDI, GETMEMUQI,
+ GETMEMUHI, GETMEMUSI, GETMEMUDI, SETMEMQI, SETMEMHI, SETMEMSI,
+ SETMEMDI, SETMEMUQI, SETMEMUHI, SETMEMUSI, SETMEMUDI): Ditto.
+
Sat May 3 08:38:55 1997 Doug Evans <dje@seba.cygnus.com>
* decode.c (decode): Add computed goto support.
if (! MEM_CHECK_ALIGNMENT (a, QI))
{ engine_signal (cpu, SIM_SIGALIGN); }
PROFILE_COUNT_READ (cpu, a, MODE_QI);
- return sim_core_read_1 (CPU_STATE (cpu), sim_core_read_map, a, NULL, NULL_CIA);
+ return sim_core_read_aligned_1 (cpu, NULL_CIA, sim_core_read_map, a);
}
#else
extern QI GETMEMQI (SIM_CPU *, ADDR);
if (! MEM_CHECK_ALIGNMENT (a, HI))
{ engine_signal (cpu, SIM_SIGALIGN); }
PROFILE_COUNT_READ (cpu, a, MODE_HI);
- return sim_core_read_2 (CPU_STATE (cpu), sim_core_read_map, a, NULL, NULL_CIA);
+ return sim_core_read_aligned_2 (cpu, NULL_CIA, sim_core_read_map, a);
}
#else
extern HI GETMEMHI (SIM_CPU *, ADDR);
if (! MEM_CHECK_ALIGNMENT (a, SI))
{ engine_signal (cpu, SIM_SIGALIGN); }
PROFILE_COUNT_READ (cpu, a, MODE_SI);
- return sim_core_read_4 (CPU_STATE (cpu), sim_core_read_map, a, NULL, NULL_CIA);
+ return sim_core_read_aligned_4 (cpu, NULL_CIA, sim_core_read_map, a);
}
#else
extern SI GETMEMSI (SIM_CPU *, ADDR);
if (! MEM_CHECK_ALIGNMENT (a, DI))
{ engine_signal (cpu, SIM_SIGALIGN); }
PROFILE_COUNT_READ (cpu, a, MODE_DI);
- return sim_core_read_8 (CPU_STATE (cpu), sim_core_read_map, a, NULL, NULL_CIA);
+ return sim_core_read_aligned_8 (cpu, NULL_CIA, sim_core_read_map, a);
}
#else
extern DI GETMEMDI (SIM_CPU *, ADDR);
if (! MEM_CHECK_ALIGNMENT (a, UQI))
{ engine_signal (cpu, SIM_SIGALIGN); }
PROFILE_COUNT_READ (cpu, a, MODE_UQI);
- return sim_core_read_1 (CPU_STATE (cpu), sim_core_read_map, a, NULL, NULL_CIA);
+ return sim_core_read_aligned_1 (cpu, NULL_CIA, sim_core_read_map, a);
}
#else
extern UQI GETMEMUQI (SIM_CPU *, ADDR);
if (! MEM_CHECK_ALIGNMENT (a, UHI))
{ engine_signal (cpu, SIM_SIGALIGN); }
PROFILE_COUNT_READ (cpu, a, MODE_UHI);
- return sim_core_read_2 (CPU_STATE (cpu), sim_core_read_map, a, NULL, NULL_CIA);
+ return sim_core_read_aligned_2 (cpu, NULL_CIA, sim_core_read_map, a);
}
#else
extern UHI GETMEMUHI (SIM_CPU *, ADDR);
if (! MEM_CHECK_ALIGNMENT (a, USI))
{ engine_signal (cpu, SIM_SIGALIGN); }
PROFILE_COUNT_READ (cpu, a, MODE_USI);
- return sim_core_read_4 (CPU_STATE (cpu), sim_core_read_map, a, NULL, NULL_CIA);
+ return sim_core_read_aligned_4 (cpu, NULL_CIA, sim_core_read_map, a);
}
#else
extern USI GETMEMUSI (SIM_CPU *, ADDR);
if (! MEM_CHECK_ALIGNMENT (a, UDI))
{ engine_signal (cpu, SIM_SIGALIGN); }
PROFILE_COUNT_READ (cpu, a, MODE_UDI);
- return sim_core_read_8 (CPU_STATE (cpu), sim_core_read_map, a, NULL, NULL_CIA);
+ return sim_core_read_aligned_8 (cpu, NULL_CIA, sim_core_read_map, a);
}
#else
extern UDI GETMEMUDI (SIM_CPU *, ADDR);
if (! MEM_CHECK_ALIGNMENT (a, QI))
{ engine_signal (cpu, SIM_SIGALIGN); return; }
PROFILE_COUNT_WRITE (cpu, a, MODE_QI);
- sim_core_write_1 (CPU_STATE (cpu), sim_core_read_map, a, val, NULL, NULL_CIA);
+ sim_core_write_aligned_1 (cpu, NULL_CIA, sim_core_read_map, a, val);
}
#else
extern void SETMEMQI (SIM_CPU *, ADDR, QI);
if (! MEM_CHECK_ALIGNMENT (a, HI))
{ engine_signal (cpu, SIM_SIGALIGN); return; }
PROFILE_COUNT_WRITE (cpu, a, MODE_HI);
- sim_core_write_2 (CPU_STATE (cpu), sim_core_read_map, a, val, NULL, NULL_CIA);
+ sim_core_write_aligned_2 (cpu, NULL_CIA, sim_core_read_map, a, val);
}
#else
extern void SETMEMHI (SIM_CPU *, ADDR, HI);
if (! MEM_CHECK_ALIGNMENT (a, SI))
{ engine_signal (cpu, SIM_SIGALIGN); return; }
PROFILE_COUNT_WRITE (cpu, a, MODE_SI);
- sim_core_write_4 (CPU_STATE (cpu), sim_core_read_map, a, val, NULL, NULL_CIA);
+ sim_core_write_aligned_4 (cpu, NULL_CIA, sim_core_read_map, a, val);
}
#else
extern void SETMEMSI (SIM_CPU *, ADDR, SI);
if (! MEM_CHECK_ALIGNMENT (a, DI))
{ engine_signal (cpu, SIM_SIGALIGN); return; }
PROFILE_COUNT_WRITE (cpu, a, MODE_DI);
- sim_core_write_8 (CPU_STATE (cpu), sim_core_read_map, a, val, NULL, NULL_CIA);
+ sim_core_write_aligned_8 (cpu, NULL_CIA, sim_core_read_map, a, val);
}
#else
extern void SETMEMDI (SIM_CPU *, ADDR, DI);
if (! MEM_CHECK_ALIGNMENT (a, UQI))
{ engine_signal (cpu, SIM_SIGALIGN); return; }
PROFILE_COUNT_WRITE (cpu, a, MODE_UQI);
- sim_core_write_1 (CPU_STATE (cpu), sim_core_read_map, a, val, NULL, NULL_CIA);
+ sim_core_write_aligned_1 (cpu, NULL_CIA, sim_core_read_map, a, val);
}
#else
extern void SETMEMUQI (SIM_CPU *, ADDR, UQI);
if (! MEM_CHECK_ALIGNMENT (a, UHI))
{ engine_signal (cpu, SIM_SIGALIGN); return; }
PROFILE_COUNT_WRITE (cpu, a, MODE_UHI);
- sim_core_write_2 (CPU_STATE (cpu), sim_core_read_map, a, val, NULL, NULL_CIA);
+ sim_core_write_aligned_2 (cpu, NULL_CIA, sim_core_read_map, a, val);
}
#else
extern void SETMEMUHI (SIM_CPU *, ADDR, UHI);
if (! MEM_CHECK_ALIGNMENT (a, USI))
{ engine_signal (cpu, SIM_SIGALIGN); return; }
PROFILE_COUNT_WRITE (cpu, a, MODE_USI);
- sim_core_write_4 (CPU_STATE (cpu), sim_core_read_map, a, val, NULL, NULL_CIA);
+ sim_core_write_aligned_4 (cpu, NULL_CIA, sim_core_read_map, a, val);
}
#else
extern void SETMEMUSI (SIM_CPU *, ADDR, USI);
if (! MEM_CHECK_ALIGNMENT (a, UDI))
{ engine_signal (cpu, SIM_SIGALIGN); return; }
PROFILE_COUNT_WRITE (cpu, a, MODE_UDI);
- sim_core_write_8 (CPU_STATE (cpu), sim_core_read_map, a, val, NULL, NULL_CIA);
+ sim_core_write_aligned_8 (cpu, NULL_CIA, sim_core_read_map, a, val);
}
#else
extern void SETMEMUDI (SIM_CPU *, ADDR, UDI);
/* FIXME:wip */
sim_core_attach (sd,
+ NULL,
attach_raw_memory,
access_read_write_exec,
0, 0, 0x100000, NULL, NULL);
print_m32r_misc_cpu (SIM_CPU *cpu, int verbose)
{
SIM_DESC sd = CPU_STATE (cpu);
+ char buf[20];
if (CPU_PROFILE_FLAGS (cpu) [PROFILE_INSN_IDX])
{
sim_io_printf (sd, "Miscellaneous Statistics\n\n");
- sim_io_printf (sd, " %-*s %ld\n\n",
+ sim_io_printf (sd, " %-*s %s\n\n",
PROFILE_LABEL_WIDTH, "Fill nops:",
- CPU_M32R_PROFILE (cpu).fillnop_count);
+ sim_add_commas (buf, sizeof (buf),
+ CPU_M32R_PROFILE (cpu).fillnop_count));
}
}
+Mon May 5 11:50:43 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * alu.h: Update usage of core object to reflect recent changes in
+ ../common/sim-*core.
+ * sim-calls.c (sim_open): Ditto.
+
Mon May 5 14:10:17 1997 Andrew Cagney <cagney@b1.cygnus.com>
* insn (cmnd): No-op cache flushes.
/* Bring data in from the cold */
#define IMEM(EA) \
-(sim_core_read_4(sd, sim_core_execute_map, (EA), \
- STATE_CPU (sd, 0), cia))
+(sim_core_read_aligned_4(STATE_CPU (sd, 0), cia, sim_core_execute_map, (EA)))
#define MEM(SIGN, EA, NR_BYTES) \
-((SIGN##_##NR_BYTES) sim_core_read_##NR_BYTES (SD, sim_core_read_map, \
- (EA) & ~(NR_BYTES - 1), \
- STATE_CPU (sd, 0), cia))
+((SIGN##_##NR_BYTES) sim_core_read_unaligned_##NR_BYTES (STATE_CPU (sd, 0), cia, \
+ sim_core_read_map, \
+ (EA)))
#define STORE(EA, NR_BYTES, VAL) \
do { \
- sim_core_write_##NR_BYTES (SD, sim_core_write_map, \
- (EA) & ~(NR_BYTES - 1), (VAL), \
- STATE_CPU (sd, 0), cia); \
+ sim_core_write_unaligned_##NR_BYTES (STATE_CPU (sd, 0), cia, \
+ sim_core_write_map, \
+ (EA), (VAL)); \
} while (0)
dnl Options available in this module
SIM_AC_OPTION_INLINE(0)
SIM_AC_OPTION_ENDIAN(LITTLE_ENDIAN)
+SIM_AC_OPTION_ALIGNMENT(FORCED_ALIGNMENT)
SIM_AC_OPTION_HOSTENDIAN
SIM_AC_OPTION_WARNINGS
SIM_AC_OPTION_RESERVED_BITS(1)
/* external memory */
sim_core_attach(&simulation,
+ NULL,
attach_raw_memory,
access_read_write_exec,
0, TIC80_MEM_START, TIC80_MEM_SIZE, NULL, NULL);
sim_core_attach(&simulation,
+ NULL,
attach_raw_memory,
access_read_write_exec,
0, 0, TIC80_MEM_SIZE, NULL, NULL);
projects / binutils-gdb.git / commitdiff