rs6000.opt (mlra): Replace with stub.

gcc/

	* config/rs6000/rs6000.opt (mlra): Replace with stub.
	* config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Delete OPTION_MASK_LRA.
	* config/rs6000/rs6000.c (TARGET_LRA_P): Delete.
	(rs6000_debug_reg_global): Delete print of LRA status.
	(rs6000_option_override_internal): Delete dead LRA related code.
	(rs6000_lra_p): Delete function.
	* doc/invoke.texi (RS/6000 and PowerPC Options): Delete -mlra.

gcc/testsuite/

	* g++.dg/pr69667.C: Remove option -mlra.
	* gcc.target/powerpc/dform-1.c: Likewise.
	* gcc.target/powerpc/dform-2.c: Likewise.
	* gcc.target/powerpc/dform-3.c: Likewise.
	* gcc.target/powerpc/p8vector-int128-1.c: Likewise.
	* gcc.target/powerpc/p9-vparity.c: Likewise.
	* gcc.target/powerpc/pr63491.c: Likewise.
	* gcc.target/powerpc/pr67808.c: Likewise.
	* gcc.target/powerpc/pr68805.c: Likewise.
	* gcc.target/powerpc/pr69461.c: Likewise.
	* gcc.target/powerpc/pr71680.c: Likewise.
	* gcc.target/powerpc/pr77289.c: Likewise.
	* gcc.target/powerpc/pr78458.c: Likewise.
	* gcc.target/powerpc/pr78543.c: Likewise.
	* g++.dg/pr71294.C: Remove option -mno-lra.
	* gcc.target/powerpc/pr71656-1.c: Likewise.
	* gcc.target/powerpc/pr71656-2.c: Likewise.
	* gcc.target/powerpc/pr71698.c: Likewise.

From-SVN: r250637

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index d8069d3ac683fc733ec0a277dece22a9abefac3e..252229e0d259993a6f826bfba4ec2c8c90e42052 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,13 @@
+2017-07-27  Peter Bergner  <bergner@vnet.ibm.com>
+
+       * config/rs6000/rs6000.opt (mlra): Replace with stub.
+       * config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Delete OPTION_MASK_LRA.
+       * config/rs6000/rs6000.c (TARGET_LRA_P): Delete.
+       (rs6000_debug_reg_global): Delete print of LRA status.
+       (rs6000_option_override_internal): Delete dead LRA related code.
+       (rs6000_lra_p): Delete function.
+       * doc/invoke.texi (RS/6000 and PowerPC Options): Delete -mlra.
+
 2017-07-27  Sebastian Huber  <sebastian.huber@embedded-brains.de>
 
        * config.gcc (riscv*-*-elf*): Add (riscv*-*-rtems*).

diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index 51aff3a5c3177f6565e14ffa58b766b4c72feea5..190f9123fa0cafcc8d429201631cd7d2987e61de 100644 (file)
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -123,7 +123,6 @@
                                 | OPTION_MASK_FPRND                    \
                                 | OPTION_MASK_HTM                      \
                                 | OPTION_MASK_ISEL                     \
-                                | OPTION_MASK_LRA                      \
                                 | OPTION_MASK_MFCRF                    \
                                 | OPTION_MASK_MFPGPR                   \
                                 | OPTION_MASK_MODULO                   \

diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 7461decd99c776af44dc8e7ef1032f1935d98c04..016a9bef2dfdf7a45124ea4b06414261b990e60b 100644 (file)
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -1887,9 +1887,6 @@ static const struct attribute_spec rs6000_attribute_table[] =
 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
 #define TARGET_MODE_DEPENDENT_ADDRESS_P rs6000_mode_dependent_address_p
 
-#undef TARGET_LRA_P
-#define TARGET_LRA_P rs6000_lra_p
-
 #undef TARGET_COMPUTE_PRESSURE_CLASSES
 #define TARGET_COMPUTE_PRESSURE_CLASSES rs6000_compute_pressure_classes
 
@@ -2790,8 +2787,6 @@ rs6000_debug_reg_global (void)
   if (TARGET_LINK_STACK)
     fprintf (stderr, DEBUG_FMT_S, "link_stack", "true");
 
-  fprintf (stderr, DEBUG_FMT_S, "lra", TARGET_LRA ? "true" : "false");
-
   if (TARGET_P8_FUSION)
     {
       char options[80];
@@ -4555,35 +4550,10 @@ rs6000_option_override_internal (bool global_init_p)
        }
     }
 
-  /* Enable LRA by default.  */
-  if ((rs6000_isa_flags_explicit & OPTION_MASK_LRA) == 0)
-    rs6000_isa_flags |= OPTION_MASK_LRA;
-
-  /* There have been bugs with -mvsx-timode that don't show up with -mlra,
-     but do show up with -mno-lra.  Given -mlra will become the default once
-     PR 69847 is fixed, turn off the options with problems by default if
-     -mno-lra was used, and warn if the user explicitly asked for the option.
-
-     Enable -mpower9-dform-vector by default if LRA and other power9 options.
-     Enable -mvsx-timode by default if LRA and VSX.  */
-  if (!TARGET_LRA)
-    {
-      if (TARGET_VSX_TIMODE)
-       {
-         if ((rs6000_isa_flags_explicit & OPTION_MASK_VSX_TIMODE) != 0)
-           warning (0, "-mvsx-timode might need -mlra");
-
-         else
-           rs6000_isa_flags &= ~OPTION_MASK_VSX_TIMODE;
-       }
-    }
-
-  else
-    {
-      if (TARGET_VSX && !TARGET_VSX_TIMODE
-         && (rs6000_isa_flags_explicit & OPTION_MASK_VSX_TIMODE) == 0)
-       rs6000_isa_flags |= OPTION_MASK_VSX_TIMODE;
-    }
+  /* Enable -mvsx-timode by default if VSX.  */
+  if (TARGET_VSX && !TARGET_VSX_TIMODE
+      && (rs6000_isa_flags_explicit & OPTION_MASK_VSX_TIMODE) == 0)
+    rs6000_isa_flags |= OPTION_MASK_VSX_TIMODE;
 
   /* Set -mallow-movmisalign to explicitly on if we have full ISA 2.07
      support. If we only have ISA 2.06 support, and the user did not specify
@@ -35876,14 +35846,6 @@ rs6000_libcall_value (machine_mode mode)
   return gen_rtx_REG (mode, regno);
 }
 
-
-/* Return true if we use LRA instead of reload pass.  */
-static bool
-rs6000_lra_p (void)
-{
-  return TARGET_LRA;
-}
-
 /* Compute register pressure classes.  We implement the target hook to avoid
    IRA picking something like NON_SPECIAL_REGS as a pressure class, which can
    lead to incorrect estimates of number of available registers and therefor

diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 1fa65a0551f61467cf77ba29ad776eb92a528c34..e94aa07bc7a5a680a24b18b44d9ef03d072e4eeb 100644 (file)
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -430,9 +430,9 @@ mlong-double-
 Target RejectNegative Joined UInteger Var(rs6000_long_double_type_size) Save
 -mlong-double-<n>      Specify size of long double (64 or 128 bits).
 
+; This option existed in the past, but now is always on.
 mlra
-Target Report Mask(LRA) Var(rs6000_isa_flags)
-Enable Local Register Allocation.
+Target RejectNegative Undocumented Ignore
 
 msched-costly-dep=
 Target RejectNegative Joined Var(rs6000_sched_costly_dep_str)

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 6e174c5b3ffb3c144cd1c103467580e21a338e27..5ae9dc4128d5bd2abc15e6b1982051b798f73b70 100644 (file)
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1048,8 +1048,7 @@ See RS/6000 and PowerPC Options.
 -mfloat128  -mno-float128  -mfloat128-hardware  -mno-float128-hardware @gol
 -mgnu-attribute  -mno-gnu-attribute @gol
 -mstack-protector-guard=@var{guard} -mstack-protector-guard-reg=@var{reg} @gol
--mstack-protector-guard-offset=@var{offset} @gol
--mlra  -mno-lra}
+-mstack-protector-guard-offset=@var{offset}}
 
 @emph{RX Options}
 @gccoptlist{-m64bit-doubles  -m32bit-doubles  -fpu  -nofpu@gol
@@ -21841,11 +21840,6 @@ This switch enables or disables the generation of ISEL instructions.
 This switch has been deprecated.  Use @option{-misel} and
 @option{-mno-isel} instead.
 
-@item -mlra
-@opindex mlra
-Enable Local Register Allocation. By default the port uses LRA.
-(i.e. @option{-mno-lra}).
-
 @item -mspe
 @itemx -mno-spe
 @opindex mspe

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 87d3b6fce2f6ea47cfaf36f9daf435b1275b4018..40f9501afb8cc63329130a534a67319b6f773900 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,24 @@
+2017-07-27  Peter Bergner  <bergner@vnet.ibm.com>
+
+       * g++.dg/pr69667.C: Remove option -mlra.
+       * gcc.target/powerpc/dform-1.c: Likewise.
+       * gcc.target/powerpc/dform-2.c: Likewise.
+       * gcc.target/powerpc/dform-3.c: Likewise.
+       * gcc.target/powerpc/p8vector-int128-1.c: Likewise.
+       * gcc.target/powerpc/p9-vparity.c: Likewise.
+       * gcc.target/powerpc/pr63491.c: Likewise.
+       * gcc.target/powerpc/pr67808.c: Likewise.
+       * gcc.target/powerpc/pr68805.c: Likewise.
+       * gcc.target/powerpc/pr69461.c: Likewise.
+       * gcc.target/powerpc/pr71680.c: Likewise.
+       * gcc.target/powerpc/pr77289.c: Likewise.
+       * gcc.target/powerpc/pr78458.c: Likewise.
+       * gcc.target/powerpc/pr78543.c: Likewise.
+       * g++.dg/pr71294.C: Remove option -mno-lra.
+       * gcc.target/powerpc/pr71656-1.c: Likewise.
+       * gcc.target/powerpc/pr71656-2.c: Likewise.
+       * gcc.target/powerpc/pr71698.c: Likewise.
+
 2017-07-27  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
            Sudakshina Das  <sudi.das@arm.com>
 

diff --git a/gcc/testsuite/g++.dg/pr69667.C b/gcc/testsuite/g++.dg/pr69667.C
index 2b3e93d2e1e36b5ebfc2834d0564c10c67880091..76f7cb3d40b3e5bc5f258c6157c1dd5d85263f11 100644 (file)
--- a/gcc/testsuite/g++.dg/pr69667.C
+++ b/gcc/testsuite/g++.dg/pr69667.C
@@ -2,7 +2,7 @@
 /* { dg-skip-if "" { powerpc*-*-darwin* } } */
 /* { dg-require-effective-target powerpc_p8vector_ok } */
 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */
-/* { dg-options "-mcpu=power8 -w -std=c++14 -mlra" } */
+/* { dg-options "-mcpu=power8 -w -std=c++14" } */
 
 /* target/69667, compiler got
    internal compiler error: Max. number of generated reload insns per insn is achieved (90)  */

diff --git a/gcc/testsuite/g++.dg/pr71294.C b/gcc/testsuite/g++.dg/pr71294.C
index 55dd01e5ccf12ab8aed79dd09a3fa0df7e444ba4..67675dd7e3060dfd61aa176f10275c1914b0da9e 100644 (file)
--- a/gcc/testsuite/g++.dg/pr71294.C
+++ b/gcc/testsuite/g++.dg/pr71294.C
@@ -1,7 +1,7 @@
 // { dg-do compile { target { powerpc64*-*-* && lp64 } } }
 // { dg-require-effective-target powerpc_p8vector_ok } */
 // { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } }
-// { dg-options "-mcpu=power8 -O3 -fstack-protector -mno-lra" }
+// { dg-options "-mcpu=power8 -O3 -fstack-protector" }
 
 // PAR target/71294 failed because RELOAD could not figure how create a V2DI
 // vector that auto vectorization created with each element being the same

diff --git a/gcc/testsuite/gcc.target/powerpc/dform-1.c b/gcc/testsuite/gcc.target/powerpc/dform-1.c
index 12623f20262cf402f33051de5d110933aa39cbd2..37a30d1c92f68ecca65e85adda190af5d53787a0 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/dform-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/dform-1.c
@@ -1,7 +1,7 @@
 /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
 /* { dg-require-effective-target powerpc_p9vector_ok } */
 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
-/* { dg-options "-mcpu=power9 -mpower9-dform -O2 -mlra" } */
+/* { dg-options "-mcpu=power9 -mpower9-dform -O2" } */
 
 #ifndef TYPE
 #define TYPE double

diff --git a/gcc/testsuite/gcc.target/powerpc/dform-2.c b/gcc/testsuite/gcc.target/powerpc/dform-2.c
index 86d65b5b1fdcec7581dae973d12b67e4c9976b9f..b4c4199c0b3d6bcddd1c0322e768882c8472e688 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/dform-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/dform-2.c
@@ -1,7 +1,7 @@
 /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
 /* { dg-require-effective-target powerpc_p9vector_ok } */
 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
-/* { dg-options "-mcpu=power9 -mpower9-dform -O2 -mlra" } */
+/* { dg-options "-mcpu=power9 -mpower9-dform -O2" } */
 
 #ifndef TYPE
 #define TYPE float

diff --git a/gcc/testsuite/gcc.target/powerpc/dform-3.c b/gcc/testsuite/gcc.target/powerpc/dform-3.c
index b1c481fbf6d1802b1da032a7a6808fb3a53f6ab1..c261c4e6f5d36bd5695ab2dc2a711ea3dc63706a 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/dform-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/dform-3.c
@@ -1,7 +1,7 @@
 /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
 /* { dg-require-effective-target powerpc_p9vector_ok } */
 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
-/* { dg-options "-mcpu=power9 -mpower9-dform -O2 -mlra" } */
+/* { dg-options "-mcpu=power9 -mpower9-dform -O2" } */
 
 #ifndef TYPE
 #define TYPE vector double

diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-int128-1.c b/gcc/testsuite/gcc.target/powerpc/p8vector-int128-1.c
index 23663b96da6a00d5c7c016ee2985bffd9a25fcaf..992ed225d5f8f70f32a08b9668ac6b0a7f61aebc 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/p8vector-int128-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/p8vector-int128-1.c
@@ -2,7 +2,7 @@
 /* { dg-skip-if "" { powerpc*-*-darwin* } } */
 /* { dg-require-effective-target powerpc_p8vector_ok } */
 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
-/* { dg-options "-mcpu=power8 -O3 -mvsx-timode -mlra" } */
+/* { dg-options "-mcpu=power8 -O3 -mvsx-timode" } */
 
 #include <altivec.h>
 

diff --git a/gcc/testsuite/gcc.target/powerpc/p9-vparity.c b/gcc/testsuite/gcc.target/powerpc/p9-vparity.c
index af5b5905a6fefa994988d150df5b33519f586b91..6e49606fe0b22c0615ab33a3fda9df6e0431d07a 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/p9-vparity.c
+++ b/gcc/testsuite/gcc.target/powerpc/p9-vparity.c
@@ -2,7 +2,7 @@
 /* { dg-skip-if "" { powerpc*-*-darwin* } } */
 /* { dg-require-effective-target powerpc_p9vector_ok } */
 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
-/* { dg-options "-mcpu=power9 -O2 -mlra -mvsx-timode" } */
+/* { dg-options "-mcpu=power9 -O2 -mvsx-timode" } */
 
 #include <altivec.h>
 

diff --git a/gcc/testsuite/gcc.target/powerpc/pr63491.c b/gcc/testsuite/gcc.target/powerpc/pr63491.c
index a151891230898388e51624abe9c383b298549824..be6a40eb32dc68b11f1eed27ca3cce97bdda0129 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/pr63491.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr63491.c
@@ -1,5 +1,5 @@
 /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
-/* { dg-options "-O1 -mcpu=power8 -mlra" } */
+/* { dg-options "-O1 -mcpu=power8" } */
 
 typedef __int128_t __attribute__((__vector_size__(16))) vector_128_t;
 typedef unsigned long long scalar_64_t;

diff --git a/gcc/testsuite/gcc.target/powerpc/pr67808.c b/gcc/testsuite/gcc.target/powerpc/pr67808.c
index 16b309c151e59e97329b982e480d0c71af6ee843..3ee8003bebc299beb374715612a8fcd1a7c7485a 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/pr67808.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr67808.c
@@ -2,7 +2,7 @@
 /* { dg-skip-if "" { powerpc*-*-darwin* } } */
 /* { dg-require-effective-target powerpc_vsx_ok } */
 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */
-/* { dg-options "-O1 -mvsx -mlra -mcpu=power7 -mlong-double-128" } */
+/* { dg-options "-O1 -mvsx -mcpu=power7 -mlong-double-128" } */
 
 /* PR 67808: LRA ICEs on simple double to long double conversion test case */
 

diff --git a/gcc/testsuite/gcc.target/powerpc/pr68805.c b/gcc/testsuite/gcc.target/powerpc/pr68805.c
index 5510811107da4e03ff33555109c360743007ae92..f4454a9e2d2e16db6554cc77442c70d4e210950f 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/pr68805.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr68805.c
@@ -1,6 +1,6 @@
 /* { dg-do compile { target powerpc64le-*-* } } */
 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
-/* { dg-options "-O2 -mvsx-timode -mcpu=power8 -mlra" } */
+/* { dg-options "-O2 -mvsx-timode -mcpu=power8" } */
 
 typedef struct bar {
   void *a;

diff --git a/gcc/testsuite/gcc.target/powerpc/pr69461.c b/gcc/testsuite/gcc.target/powerpc/pr69461.c
index 406e7049d2994f381c911621c39404680ceed21b..f693a5f0146818ebfd4e895e8072e9b825a291c8 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/pr69461.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr69461.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O3 -mlra" } */
+/* { dg-options "-O3" } */
 
 extern void _setjmp (void);
 typedef struct {

diff --git a/gcc/testsuite/gcc.target/powerpc/pr71656-1.c b/gcc/testsuite/gcc.target/powerpc/pr71656-1.c
index fa6b4ffb81694f16ba89b7f54ce5e7fb771dfb54..1cb809f8b2a976f073ee4071a61b7db22b52f5ab 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/pr71656-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr71656-1.c
@@ -2,7 +2,7 @@
 /* { dg-do compile } */
 /* { dg-require-effective-target powerpc_p9vector_ok } */
 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
-/* { dg-options "-O1 -mcpu=power9 -mpower9-dform-vector -mno-lra" } */
+/* { dg-options "-O1 -mcpu=power9 -mpower9-dform-vector" } */
 
 typedef __attribute__((altivec(vector__))) int type_t;
 type_t

diff --git a/gcc/testsuite/gcc.target/powerpc/pr71656-2.c b/gcc/testsuite/gcc.target/powerpc/pr71656-2.c
index 99855fa1667c2ad6d292438bfc63583b87445099..f953ebe4f9e4b934587c85c7c96df4b986f018fa 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/pr71656-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr71656-2.c
@@ -2,7 +2,7 @@
 /* { dg-do compile } */
 /* { dg-require-effective-target powerpc_p9vector_ok } */
 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
-/* { dg-options "-O3 -mcpu=power9 -mpower9-dform-vector -mno-lra -funroll-loops -fno-aggressive-loop-optimizations" } */
+/* { dg-options "-O3 -mcpu=power9 -mpower9-dform-vector -funroll-loops -fno-aggressive-loop-optimizations" } */
 
 typedef double vec[3];
 struct vec_t

diff --git a/gcc/testsuite/gcc.target/powerpc/pr71680.c b/gcc/testsuite/gcc.target/powerpc/pr71680.c
index fe5260f73d970312fa885e6a88a9ea1b8213fb2f..cdb7b5143edddabb23d193cd79803bf360e6ae9d 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/pr71680.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr71680.c
@@ -1,7 +1,7 @@
 /* { dg-do compile { target { powerpc*-*-* } } } */
 /* { dg-require-effective-target powerpc_vsx_ok } */
 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
-/* { dg-options "-mcpu=power8 -O1 -mlra" } */
+/* { dg-options "-mcpu=power8 -O1" } */
 
 #pragma pack(1)
 struct

diff --git a/gcc/testsuite/gcc.target/powerpc/pr71698.c b/gcc/testsuite/gcc.target/powerpc/pr71698.c
index c752f64e1c7667aeb4a22bfbda5a45ff59110d47..eba47b0951f59d7c05c23d6d1739e008b59f2c17 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/pr71698.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr71698.c
@@ -3,7 +3,7 @@
 /* { dg-require-effective-target powerpc_p9vector_ok } */
 /* { dg-require-effective-target dfp } */
 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
-/* { dg-options "-O1 -mcpu=power9 -mno-lra" } */
+/* { dg-options "-O1 -mcpu=power9" } */
 
 extern void testvad128 (int n, ...);
 void

diff --git a/gcc/testsuite/gcc.target/powerpc/pr77289.c b/gcc/testsuite/gcc.target/powerpc/pr77289.c
index 295aa27acdc8c951c029b4038739bf89e61d4ad2..474bdbf0b16753a5363d252eeadec3406025a802 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/pr77289.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr77289.c
@@ -2,7 +2,7 @@
 /* { dg-skip-if "" { powerpc*-*-darwin* } } */
 /* { dg-require-effective-target powerpc_vsx_ok } */
 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */
-/* { dg-options "-O3 -mcpu=power7 -funroll-loops -ffast-math -mlra -mupdate -fno-auto-inc-dec" } */
+/* { dg-options "-O3 -mcpu=power7 -funroll-loops -ffast-math -mupdate -fno-auto-inc-dec" } */
 
 /* PR 77289: LRA ICEs due to invalid constraint checking.  */
 

diff --git a/gcc/testsuite/gcc.target/powerpc/pr78458.c b/gcc/testsuite/gcc.target/powerpc/pr78458.c
index 777ac43bcadcf38df58a1584dc831bbd1266ea27..a27876375af00a9eb8e75d5df45e5bf0c63827b1 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/pr78458.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr78458.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mcpu=8548 -mspe -mabi=spe -mlra" } */
+/* { dg-options "-mcpu=8548 -mspe -mabi=spe" } */
 /* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } } */
 
 extern void bar (void);

diff --git a/gcc/testsuite/gcc.target/powerpc/pr78543.c b/gcc/testsuite/gcc.target/powerpc/pr78543.c
index 0421344d3cedf614148a6504e9ade151f6aa921c..13b34e58a0beed9e78aa10d611d7d8acc162cf3d 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/pr78543.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr78543.c
@@ -1,7 +1,7 @@
 /* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
 /* { dg-require-effective-target powerpc_p8vector_ok } */
 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
-/* { dg-options "-mcpu=power8 -O1 -mno-lra" } */
+/* { dg-options "-mcpu=power8 -O1" } */
 
 typedef long a;
 enum c { e, f, g, h, i, ab } j();