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update todo
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Wed, 21 Mar 2018 17:10:08 +0000
(17:10 +0000)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Wed, 21 Mar 2018 17:10:08 +0000
(17:10 +0000)
shakti/m_class/todo.mdwn
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diff --git
a/shakti/m_class/todo.mdwn
b/shakti/m_class/todo.mdwn
index bee2cc768de646bd633e762d1a044005ab9dfe36..2671bf61dde3a227938b979bb2c1cff624cb2761 100644
(file)
--- a/
shakti/m_class/todo.mdwn
+++ b/
shakti/m_class/todo.mdwn
@@
-7,7
+7,8
@@
Issues tracked on <http://bugs.libre-riscv.org>
## RISC-V team
* RV64GC SMP Core
-* Analyse and decide L1 / L2 cache sizes
+* Analyse and decide L1 / L2 cache sizes (*underway*)
+* Quad SPI (down-compatible to 1-bit SPI) (*done*) [[QSPI]]
## Richard Herveille
@@
-20,10
+21,9
@@
Issues tracked on <http://bugs.libre-riscv.org>
## TBD
-* 1/2/4-bit SD/MMC
-* eMMC (8-bit SD/MMC)
+* 1/2/4-bit SD/MMC
(Rudi?)
+* eMMC (8-bit SD/MMC)
(Rudi?)
* DDR3/DDR4 PHY
-* Quad SPI (down-compatible to 1-bit SPI)
* Pinmux (underway)
* Video Processing Block
* 3D Engine (Nyuzi?)