i965/vp: Remove support for GLSL flow control from the old VS backend.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c
index 46954bc4c00c636fb84b25530f06a8427b4c63fb..b2b59bc69d2e0a4e0b144ad60f90f2512a79d994 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vs_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c
@@ -1766,43 +1766,6 @@ accumulator_contains(struct brw_vs_compile *c, struct brw_reg val)
    }
 }
 
-static uint32_t
-get_predicate(const struct prog_instruction *inst)
-{
-   if (inst->DstReg.CondMask == COND_TR)
-      return BRW_PREDICATE_NONE;
-
-   /* All of GLSL only produces predicates for COND_NE and one channel per
-    * vector.  Fail badly if someone starts doing something else, as it might
-    * mean infinite looping or something.
-    *
-    * We'd like to support all the condition codes, but our hardware doesn't
-    * quite match the Mesa IR, which is modeled after the NV extensions.  For
-    * those, the instruction may update the condition codes or not, then any
-    * later instruction may use one of those condition codes.  For gen4, the
-    * instruction may update the flags register based on one of the condition
-    * codes output by the instruction, and then further instructions may
-    * predicate on that.  We can probably support this, but it won't
-    * necessarily be easy.
-    */
-   assert(inst->DstReg.CondMask == COND_NE);
-
-   switch (inst->DstReg.CondSwizzle) {
-   case SWIZZLE_XXXX:
-      return BRW_PREDICATE_ALIGN16_REPLICATE_X;
-   case SWIZZLE_YYYY:
-      return BRW_PREDICATE_ALIGN16_REPLICATE_Y;
-   case SWIZZLE_ZZZZ:
-      return BRW_PREDICATE_ALIGN16_REPLICATE_Z;
-   case SWIZZLE_WWWW:
-      return BRW_PREDICATE_ALIGN16_REPLICATE_W;
-   default:
-      _mesa_problem(NULL, "Unexpected predicate: 0x%08x\n",
-                   inst->DstReg.CondMask);
-      return BRW_PREDICATE_NORMAL;
-   }
-}
-
 static void
 brw_vs_rescale_gl_fixed(struct brw_vs_compile *c)
 {
@@ -1827,11 +1790,7 @@ brw_vs_rescale_gl_fixed(struct brw_vs_compile *c)
  */
 void brw_old_vs_emit(struct brw_vs_compile *c )
 {
-#define MAX_IF_DEPTH 32
-#define MAX_LOOP_DEPTH 32
    struct brw_compile *p = &c->func;
-   struct brw_context *brw = p->brw;
-   struct intel_context *intel = &brw->intel;
    const GLuint nr_insns = c->vp->program.Base.NumInstructions;
    GLuint insn;
    GLuint index;
@@ -2051,49 +2010,7 @@ void brw_old_vs_emit(struct brw_vs_compile *c )
       case OPCODE_XPD:
         emit_xpd(p, dst, args[0], args[1]);
         break;
-      case OPCODE_IF: {
-        struct brw_instruction *if_inst = brw_IF(p, BRW_EXECUTE_8);
-        /* Note that brw_IF smashes the predicate_control field. */
-        if_inst->header.predicate_control = get_predicate(inst);
-        break;
-      }
-      case OPCODE_ELSE:
-        clear_current_const(c);
-        brw_ELSE(p);
-        break;
-      case OPCODE_ENDIF:
-        clear_current_const(c);
-        brw_ENDIF(p);
-        break;                 
-      case OPCODE_BGNLOOP:
-        clear_current_const(c);
-        brw_DO(p, BRW_EXECUTE_8);
-         break;
-      case OPCODE_BRK:
-        brw_set_predicate_control(p, get_predicate(inst));
-        brw_BREAK(p);
-        brw_set_predicate_control(p, BRW_PREDICATE_NONE);
-         break;
-      case OPCODE_CONT:
-        brw_set_predicate_control(p, get_predicate(inst));
-        if (intel->gen >= 6) {
-           gen6_CONT(p);
-        } else {
-           brw_CONT(p);
-        }
-         brw_set_predicate_control(p, BRW_PREDICATE_NONE);
-         break;
-
-      case OPCODE_ENDLOOP:
-        clear_current_const(c);
-        brw_WHILE(p);
-         break;
 
-      case OPCODE_BRA:
-        brw_set_predicate_control(p, get_predicate(inst));
-         brw_ADD(p, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16));
-        brw_set_predicate_control(p, BRW_PREDICATE_NONE);
-         break;
       case OPCODE_END:
         emit_vertex_write(c);
          break;