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radeonsi: fix compute-based culling regression in 1ce52c1e373
author
Marek Olšák
<marek.olsak@amd.com>
Tue, 16 Jul 2019 23:04:48 +0000
(19:04 -0400)
committer
Marek Olšák
<marek.olsak@amd.com>
Sat, 20 Jul 2019 00:16:50 +0000
(20:16 -0400)
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
src/gallium/drivers/radeonsi/si_state_draw.c
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diff --git
a/src/gallium/drivers/radeonsi/si_state_draw.c
b/src/gallium/drivers/radeonsi/si_state_draw.c
index f39b7c653e50c23bd128d42b55f48311088d852a..a099805e43d35e324885daa499d1933e0700e6d6 100644
(file)
--- a/
src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/
src/gallium/drivers/radeonsi/si_state_draw.c
@@
-759,7
+759,7
@@
static void si_emit_draw_registers(struct si_context *sctx,
bool primitive_restart)
{
struct radeon_cmdbuf *cs = sctx->gfx_cs;
- unsigned vgt_prim = si_conv_pipe_prim(
info->mode
);
+ unsigned vgt_prim = si_conv_pipe_prim(
prim
);
if (sctx->chip_class >= GFX10)
gfx10_emit_ge_cntl(sctx, num_patches);