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Use %precedence in verilog_parser.y
author
Claire Wolf
<claire@symbioticeda.com>
Wed, 15 Jul 2020 09:54:28 +0000
(11:54 +0200)
committer
Claire Wolf
<claire@symbioticeda.com>
Wed, 15 Jul 2020 09:54:28 +0000
(11:54 +0200)
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
frontends/verilog/verilog_parser.y
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diff --git
a/frontends/verilog/verilog_parser.y
b/frontends/verilog/verilog_parser.y
index 390ef07e9e196d1a0a16527badb855b8d0949448..63f0341d9bd645caac337d1b6b3d79f362182254 100644
(file)
--- a/
frontends/verilog/verilog_parser.y
+++ b/
frontends/verilog/verilog_parser.y
@@
-299,14
+299,14
@@
static void rewriteAsMemoryNode(AstNode *node, AstNode *rangeNode)
%left '+' '-'
%left '*' '/' '%'
%left OP_POW
-%
left
OP_CAST
-%
right
UNARY_OPS
+%
precedence
OP_CAST
+%
precedence
UNARY_OPS
%define parse.error verbose
%define parse.lac full
-%
nonassoc
FAKE_THEN
-%
nonassoc
TOK_ELSE
+%
precedence
FAKE_THEN
+%
precedence
TOK_ELSE
%debug
%locations