soc/integration/soc_dram: sync with litedram

diff --git a/litex/soc/integration/soc_sdram.py b/litex/soc/integration/soc_sdram.py
index 9c344dbfbe31f54847aa63784c6b3b6cf6e8e2a5..b9c70f710ecba0b4330e8b904c370f0601c12a35 100644 (file)
--- a/litex/soc/integration/soc_sdram.py
+++ b/litex/soc/integration/soc_sdram.py
@@ -25,7 +25,7 @@ class ControllerInjector(Module, AutoCSR):
                                                                           controller_settings)
         self.comb += controller.dfi.connect(self.dfii.slave)
 
-        self.submodules.crossbar = crossbar.LiteDRAMCrossbar(controller.lasmic, controller.nrowbits)
+        self.submodules.crossbar = crossbar.LiteDRAMCrossbar(controller.interface, controller.nrowbits)
 
 
 class SoCSDRAM(SoCCore):