Fix ECP5PLL VCO frequency range

See https://www.latticesemi.com/view_document?document_id=50461 ("ECP5
and ECP5-5G Family Data Sheet"), section 3.19 "sysCLOCK PLL Timing".

diff --git a/litex/soc/cores/clock.py b/litex/soc/cores/clock.py
index cab8bfcefe26c185f0c26febcd2198bf1fe1f63d..63a9edaa63344fb39483d4c9f1f07a4125133d1c 100644 (file)
--- a/litex/soc/cores/clock.py
+++ b/litex/soc/cores/clock.py
@@ -507,7 +507,7 @@ class ECP5PLL(Module):
     clko_div_range  = (1, 128+1)
     clki_freq_range = (    8e6,  400e6)
     clko_freq_range = (3.125e6,  400e6)
-    vco_freq_range  = (  550e6, 1250e6)
+    vco_freq_range  = (  400e6,  800e6)
 
     def __init__(self):
         self.reset      = Signal()